Capacitance model
Depending on the magnitude of the time-varying voltages, the dynamic operation can be classified as large signal operation or small signal operation.
a capacitance model describing the intrinsic and extrinsic components of the device capacitance, is another essential part of a compact MOSFET model for circuit simulation besides the DC model.
Generally, MOSFET capacitance can be divided into two groups, the intrinsic and the extrinsic capacitances.
The intrinsic capacitance is related to the region between the metallurgical source and drain junctions.
The extrinsic capacitance, or the parasitic capacitance, is further divided into five components:
1) the outer fringing capacitance between the polysilicon gate and the source/drain, CFO;
2) the inner fringing capacitance between the polysilicon gate and the source/drain, CFI;
3) the overlap capacitances between the gate and the heavily doped S/D regions (and the bulk region), CGSO & CGDO (CGBO) , which are relatively insensitive to terminal voltages;
4) the overlap capacitances between the gate and lightly doped S/D region, CGSOL & CGDOL , which changes with bias;
5) the source/drain junction capacitances, CJ D & CJS.
Intrinsic capacitance: use Meyer model(大信号模型)
Shortcoming of the Meyer model
- it has been found to yield non-physical results when used to simulate circuits that have charge storage nodes.
- Charge built-up on these nodes are incorrectly predicted by the simulation. This problem shows up in MOS charge pumps, silicon-on-sapphire(SOS) circuits, static RAM and switched-capacitor circuits. It is termed the charge non-conservation problem.
Extrinsic Capacitance Model：
把Cfo,Cfi,Cov加起来就是Covt。就是外部电容。
以上模型不适用于短沟道器件。
所以用Bsim自带的三种，三种就不写了。以后要用那个再看！