The semaphore module can be used as an arbiter to ensure mutual exclusivity when sharing resources over multiple cores in a multicore device. It provides up to 64 independent semaphores that can be acquired and released by the application.
Architecture
Each of the 64 semaphores is controlled by either reading from or writing to one of the three registers:
SEM_DIRECT, SEM_INDIRECT, or
SEM_QUERY. These three registers form a set and each semaphore is attached to one such set
. The semaphore module
can service requests using one of three methods: the direct request method, the indirect request method, or the combined request method. These three methods provide flexibility to the application to either implement
a polling-based system or
an interrupt-based callback mechanism for acquiring or locking a semaphore. None of the 64 semaphores on the module are mapped to any resource or module on the device. The application can choose to map any of the available semaphores to protect any resource.
There is no support provided by the semaphore module to store the semaphore to resource mapping information. The mapping information must be maintained by the software application.
Software Reset Considerations:
The semaphore module can be reset through software by writing to the reset bit of the
SEM_RST_RUN register. On reset, all semaphores are in ‘FREE’ state and all the errors cleared.
Hardware Reset Considerations:
On reset, all semaphores are in ‘FREE’ state and all the errors cleared.
Interrupt Events and Requests:
The semaphore module can generate an interrupt to any of the cores on the device either to signal semaphore grant or an error. The module generates two sets of interrupts: semaphore grant (SEMINTn) and error (SEMERRn). Each set
has the capability to interrupt any core (0-N) on the device. The SEMINTn interrupt is routed to the interrupt controller (INTC) of each core while the SEMERRn is routed to the respective chip interrupt controller (CIC[n]).
DMA Event Support:
All ‘N’ semaphore grant events (SEMINTn) can be used to trigger a DMA channel.The error events (SEMERRn) may be used to trigger DMA by using the TPCC interrupt controllers (CIC3) in conjunction with the CIC[n].
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