基于FPGA的等精度测频方法
1、多周期等精度测频的时序 
预置闸门时间产生电路产生预置闸门时间TP，TP经同步电路产生与被测信号（fx）同步的实际闸门时间T。
预置闸门时间产生电路产生预置闸门时间TP，TP经同步电路产生与被测信号（fx）同步的实际闸门时间T。主门Ⅰ与主门Ⅱ在时间T内被同时打开，计数器Ⅰ和Ⅱ分别对 fx和 f0 进行计数。
2、实现
1. 闸门信号与被测信号同步
2. 在闸门信号与被测信号的同步下降沿锁存计数值
3、Verilog硬件描述语言
/* 
* Copyright (C) 2009, Electric & Electronic Innovation Center of Sci. & Tech. HUST * All Rights Reserved. * * File name: mesureFreq.v * File description: Measure the frequency * Operating environment: QUARTUS II 8.1,cyclone II EP2C8Q208C8N * * This version: 1.0 * Author: lwpo2008([email protected]) * Previous Author: none * Complete date: 2009-08-20 * 
*/ 
module mesureFreq ( input fx, input fbase, input fgate, output reg[31:0] fxCnt, output reg[31:0] fbaseCnt ); reg startCnt; reg[31:0] fxCntTemp,fbaseCntTemp; always @ (posedge fbase) begin if(startCnt) fbaseCntTemp <= fbaseCntTemp + 1; else fbaseCntTemp <= 32‘h00000000; end always @ (posedge fx) begin if(startCnt) fxCntTemp <= fxCntTemp + 1; else fxCntTemp <= 32‘h00000000; end //synchronous fgate always @ (posedge fx) begin if(fgate) startCnt <= 1‘b1; else startCnt <= 1‘b0; end //output always @ (negedge startCnt) begin fxCnt <= fxCntTemp; fbaseCnt <= fbaseCntTemp; end endmodule
4、综合后逻辑电路
工程文件：/Files/lwpo2008/mesureFreq.rar