verilog behavioral modeling--sequential and parallel statements

1.Sequential statement groups

the begin-end keywords:

.group several statements togethor

.cause the statements to be evaluated sequentially(one at a time)

*any timing within the sequential groups is relative to the previous statement

*delays in the sequential accumulate(each delay is added to the previous delay)

*block finishes after the last statement in the block

Example - sequential
  1 module sequential();
  2
  3 reg a;
  4
  5 initial begin
  6   $monitor ("%g a = %b", $time, a);
  7    #10 a = 0;
  8    #11 a = 1;
  9    #12 a = 0;
10    #13 a = 1;
11    #14 $finish;
12 end
13
14 endmodule

 0 a = x
 10 a = 0
 21 a = 1
 33 a = 0
 46 a = 1

2.parallel statement groups

The fork-join keywords:

.group several statements together:

.cause the statements to evaluated in parallel(all at the same time)

*timing within parallel group is absolute to the begining of the group.

*block finishes after the last statement completes(statement with highest delay ,it can be the first statement in the block).

Example - Parallel

1 module parallel();
  2
  3 reg a;
  4
  5 initial
  6 fork
  7   $monitor ("%g a = %b", $time, a);
  8    #10 a = 0;
  9    #11 a = 1;
10    #12 a = 0;
11    #13 a = 1;
12    #14 $finish;
13 join
14
15 endmodule

Simulator Output

0 a = x
10 a = 0
11 a = 1
12 a = 0
13 a = 1

Example - Mixing "begin-end" and "fork - join"

1 module fork_join();
  2
  3 reg clk,reset,enable,data;
  4
  5 initial  begin
  6   $display ("Starting simulation");
  7   $monitor("%g clk=%b reset=%b enable=%b data=%b",
  8     $time, clk, reset, enable, data);
  9   fork : FORK_VAL
10      #1 clk = 0;
11      #5 reset = 0;
12      #5 enable = 0;
13      #2 data = 0;
14   join
15    #10 $display ("%g Terminating simulation", $time);
16   $finish;
17 end
18
19 endmodule

Simulator Output

 0 clk=x reset=x enable=x data=x
 1 clk=0 reset=x enable=x data=x
 2 clk=0 reset=x enable=x data=0
 5 clk=0 reset=0 enable=0 data=0
 15 Terminating simulation