1 `timescale 1ns / 1ps
2 //////////////////////////////////////////////////////////////////////////////////
3 // Company:
4 // Engineer:
5 //
6 // Create Date: 13:33:13 10/23/2015
7 // Design Name:
8 // Module Name: adc_test
9 // Project Name:
10 // Target Devices:
11 // Tool versions:
12 // Description:
13 //
14 // Dependencies:
15 //
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 //
20 //////////////////////////////////////////////////////////////////////////////////
21 module adc_test
22 (
23 input sys_clk,
24 input sys_rst,
25
26 input [9:0] adc_din,
27 input adc_finish,
28
29 output adc_enb,
30 output adc_samp_en,
31 output adc_go,
32 output adc_samp,
33 output adc_clk,
34 output [2:0] adc_M_out,
35
36 //inout sda,
37 //output scl,
38
39 // input uart_rx,
40 output uart_tx
41 );
42
43
44 reg [7:0] tx_data;
45 reg tx_en;
46 wire tx_done;
47 uart_tx U1
48 (
49 .sys_clk(sys_clk),
50 .rst(sys_rst),
51 .tx_en(tx_en),
52 .tx_data(tx_data),
53 .tx_done(tx_done),
54 .tx_pin_out(uart_tx)
55 );
56
57 /*wire [11:0] adc_out;
58
59 adc_module U2
60 (
61 .sys_clk(sys_clk),//100MHz
62 .rst_n(sys_rst),
63
64 .sda(sda),
65 .scl(scl),
66 .data(adc_out)
67 );
68
69 wire adc_enb_1;
70
71 wire [2:0] M_in;
72
73 wire [9:0] adc_out1;
74 adc_test_module U3
75 (
76 .sys_clk(sys_clk),
77 .sys_rst(sys_rst),
78
79 .adc_din(adc_din),
80 .adc_finish(adc_finish),
81
82 .adc_enb(adc_enb_1),
83 .adc_samp_en(adc_samp_en),
84 .adc_go(adc_go),
85 .adc_samp(adc_samp),
86 .adc_clk(adc_clk),
87
88 .adc_out(adc_out1),
89 .M_out(M_in)
90
91 );
92
93
94 reg L2H_F1;
95 reg L2H_F2;
96 reg L2H_sw;
97 reg L2H_sw1;
98 wire L2H_Sig;
99
100 always @(posedge sys_clk)
101 begin
102 if(sys_rst)begin
103 L2H_F1 <= 1‘b1;
104 L2H_F2 <= 1‘b1;
105 end else begin
106 L2H_F1 <= adc_enb_1;
107 L2H_F2 <= L2H_F1;
108
109 end
110 end
111 assign L2H_Sig = !L2H_F1 & L2H_F2;
112 */
113 reg [2:0] state;
114 reg [7:0] tx_L;
115 reg [7:0] tx_H;
116 reg [7:0] tx_H2;
117 reg tx_start;
118 reg [15:0]delay_cont;
119 reg adc_io;
120 wire [9:0]adc_data;
121 reg [11:0]adc_data0;
122 reg [11:0]adc_data1;
123 //reg [11:0]adc_data2;
124 //reg [11:0]adc_data3;
125 wire [11:0]adc_data5;
126 assign adc_data5 = adc_out;
127 wire [11:0]adc_data4;
128 reg adc_data0_0;
129 //assign adc_data = {~adc_out};
130 reg uart_out = 0;
131 reg [15:0] M_delay = 0;
132 always @(posedge sys_clk)
133 begin
134 if(L2H_F1 & !L2H_F2)begin
135 case(M_in)
136 3‘d0:begin
137 adc_data0 <={adc_data[9:0],2‘b00};
138 // adc_data0_0 <= adc_data0[2];
139 end
140 3‘d1:begin
141 adc_data1[0] <= {adc_data[0]};
142 // adc_data0_0 <=adc_data0[2:2];
143 end
144 3‘d3:begin
145 adc_data1[1] <= {adc_data[0]};
146 end
147 3‘d7:begin
148 adc_data1[2] <= {adc_data[0]};
149 uart_out <= 1;
150 end
151 endcase
152 end
153 else begin
154 uart_out <= 0;
155 end
156 end
157 //assign adc_data4 = adc_data0[2] ? ((!adc_data1[0]) + (!adc_data1[1]) + (!adc_data1[2])) : (adc_data1[0] + adc_data1[1] + adc_data1[2]);
158 //assign adc_data5 = adc_data4 + adc_data0;
159
160 always @(posedge sys_clk)
161 begin
162 if(sys_rst)begin
163 tx_en <= 1‘b0;
164 state <= 3‘d0;
165 tx_start <= 1‘d0;
166 delay_cont <= 16‘d0;
167 adc_io <= 1‘b1;
168 end else begin
169 if(uart_out)begin
170 state <= 3‘d0;
171 delay_cont <= 16‘d0;
172 tx_start <= 1‘d1;
173 end else begin
174 case(state)
175 3‘d0:
176 begin
177 // adc_data4 <= adc_data0 + adc_data0[2] + adc_data1[2] + adc_data2[2] + adc_data3[2];
178 delay_cont <= delay_cont + 16‘d1;
179 if(delay_cont == 16‘d32000) begin
180 delay_cont <= 16‘d0;
181 state <= 3‘d1;
182
183 case(adc_data5[3:0])
184 4‘d0: tx_L <= 8‘h30;
185 4‘d1: tx_L <= 8‘h31;
186 4‘d2: tx_L <= 8‘h32;
187 4‘d3: tx_L <= 8‘h33;
188 4‘d4: tx_L <= 8‘h34;
189 4‘d5: tx_L <= 8‘h35;
190 4‘d6: tx_L <= 8‘h36;
191 4‘d7: tx_L <= 8‘h37;
192 4‘d8: tx_L <= 8‘h38;
193 4‘d9: tx_L <= 8‘h39;
194 4‘d10: tx_L <= 8‘h41;
195 4‘d11: tx_L <= 8‘h42;
196 4‘d12: tx_L <= 8‘h43;
197 4‘d13: tx_L <= 8‘h44;
198 4‘d14: tx_L <= 8‘h45;
199 4‘d15: tx_L <= 8‘h46;
200 default:begin tx_L <= 8‘h58;end
201 endcase
202 case(adc_data5[7:4])
203 4‘d0: begin tx_H <= 8‘h30; end
204 4‘d1:begin tx_H <= 8‘h31;end
205 4‘d2:begin tx_H <= 8‘h32;end
206 4‘d3:begin tx_H <= 8‘h33;end
207 4‘d4:begin tx_H <= 8‘h34;end
208 4‘d5:begin tx_H <= 8‘h35;end
209 4‘d6:begin tx_H <= 8‘h36;end
210 4‘d7:begin tx_H <= 8‘h37;end
211 4‘d8:begin tx_H <= 8‘h38;end
212 4‘d9:begin tx_H <= 8‘h39;end
213 4‘d10:begin tx_H <= 8‘h41;end
214 4‘d11:begin tx_H <= 8‘h42;end
215 4‘d12:begin tx_H <= 8‘h43;end
216 4‘d13:begin tx_H <= 8‘h44;end
217 4‘d14:begin tx_H <= 8‘h45;end
218 4‘d15:begin tx_H <= 8‘h46;end
219 default:begin tx_H <= 8‘h58;end
220 endcase
221 case(adc_data5[11:8])
222 4‘d0: tx_H2 <= 8‘h30;
223 4‘d1: tx_H2 <= 8‘h31;
224 4‘d2: tx_H2 <= 8‘h32;
225 4‘d3: tx_H2 <= 8‘h33;
226 4‘d4: tx_H2 <= 8‘h34;
227 4‘d5: tx_H2 <= 8‘h35;
228 4‘d6: tx_H2 <= 8‘h36;
229 4‘d7: tx_H2 <= 8‘h37;
230 4‘d8: tx_H2 <= 8‘h38;
231 4‘d9: tx_H2 <= 8‘h39;
232 4‘d10: tx_H2 <= 8‘h41;
233 4‘d11: tx_H2 <= 8‘h42;
234 4‘d12: tx_H2 <= 8‘h43;
235 4‘d13: tx_H2 <= 8‘h44;
236 4‘d14: tx_H2 <= 8‘h45;
237 4‘d15: tx_H2 <= 8‘h46;
238 default:tx_H2 <= 8‘h58;
239 endcase
240 adc_io <= 1‘b1;
241 end else if(delay_cont == 16‘d1000) begin
242 adc_io <= 1‘b0;
243 end else begin
244 delay_cont <= delay_cont + 16‘d1;
245 end
246 end
247
248 3‘d1:
249 begin
250 if(tx_start == 1‘d1)
251 begin
252 tx_en <= 1‘b1;
253 tx_data <= tx_H2;
254 tx_start <= 1‘d0;
255 end else if(tx_done) begin
256 tx_en <= 1‘b0;
257 tx_start <= 1‘d1;
258 state <= state +3‘d1;
259 end
260 end
261 3‘d2:
262 begin
263 if(tx_start == 1‘d1)
264 begin
265 tx_en <= 1‘b1;
266 tx_data <= tx_H;
267 tx_start <= 1‘d0;
268 end else if(tx_done) begin
269 tx_en <= 1‘b0;
270 tx_start <= 1‘d1;
271 state <= state +3‘d1;
272 end
273 end
274 3‘d3:
275 begin
276 if(tx_start == 1‘d1)
277 begin
278 tx_en <= 1‘b1;
279 tx_data <= tx_L;
280 tx_start <= 1‘d0;
281 end else if(tx_done) begin
282 tx_en <= 1‘b0;
283 tx_start <= 1‘d1;
284 state <= state +3‘d1;
285 end
286 end
287 3‘d4:
288 begin
289 if(tx_start == 1‘d1)
290 begin
291 tx_en <= 1‘b1;
292 tx_data <= 8‘h0A;
293 tx_start <= 1‘d0;
294 end else if(tx_done) begin
295 tx_en <= 1‘b0;
296 tx_start <= 1‘d1;
297 state <= state +3‘d1;
298 end
299 end
300 3‘d5:
301 begin
302 if(tx_start == 1‘d1)
303 begin
304 tx_en <= 1‘b1;
305 tx_data <= 8‘h0d;
306 tx_start <= 1‘d0;
307 end else if(tx_done) begin
308 tx_en <= 1‘b0;
309 tx_start <= 1‘d1;
310 state <= 3‘d6;
311 end
312 end
313 default: state <= 3‘d6;
314 endcase
315 end
316 end
317 end
318 assign adc_enb = adc_io;
319 assign adc_M_out = M_in;
320 endmodule
时间： 2024-10-07 06:41:43