Verilog(二) register and net

1  register = storage

keyword reg;　　default x;　　variable that can hold value

2  net = connection

keyword wire;　　default z;　　be driven continuously

例 1)  D flip-flop with syn reset

module  dff(clk, rst, d, q);
  input  clk,  rst,  d;
  output  q;
  reg  q;

always @(posedge clk)
begin
  if (rst)
      q <= 1‘b0;
   else
      q <= d;
end

endmodule 

syn

例 2)  D flip-flop with asyn reset

module  dff(clk, rst, d, q);
  input  clk,  rst,  d;
  output  q;
  reg  q;

always @(posedge clk or posedge rst)
begin
  if (rst)
      q <= 1‘b0;
  else
      q <= d;
end

endmodule 

asyn