/***************************************************
/ Shift Register module
/ Programing by seongki
***************************************************/
module Shift_Register_4_beh(output reg [3:0] A_par,input [3:0] I_par, input s1,s0, MSB_in,LSB_in,CLK,Clear);
[email protected](posedge CLK,negedge Clear)
if(~Clear)A_par<=4‘b0000;
else
case({s1,s0})
2‘b00:A_par<=I_par;
2‘b01:A_par<={MSB_in,I_par[3:1]};
2‘b10:A_par<={I_par[2:0],LSB_in};
2‘b11:A_par<=I_par;
endcase
endmodule
// testbench
`timescale 1ns/1ns
module tb_Shift_Register_4_beh;
reg [3:0] I_par;
reg s1,s0,MSB_in,LSB_in,CLK,Clear;
wire [3:0] A_par;
Shift_Register_4_beh test1(A_par,I_par,s1,s0, MSB_in,LSB_in,CLK,Clear);
initial
begin
I_par=4‘b1111;
Clear=0; MSB_in=0; LSB_in=0; CLK=0; s1=0; s0=0;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=0; s0=0;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=0; s0=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=1; s0=0;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 Clear=1; MSB_in=0; LSB_in=0; CLK=0; s1=1; s0=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
#10 CLK=1;
#10 CLK=0;
end
endmodule