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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity clock60 is
    port(
        CLK : in std_logic;    --clear
        CLR : in std_logic;    --clock
        s1 : out std_logic_vector(3 downto 0);    --1
        s10 : out std_logic_vector(3 downto 0);    --10
        c0 : out std_logic    --adder of it
    );
end clock60;

architecture art of clock60 is
    signal tmp1 : std_logic_vector(3 downto 0);
    signal tmp10 : std_logic_vector(2 downto 0);
begin
    process(CLK, CLR)
    begin
        if(CLR = ‘1‘) then
            tmp1 <= "0000";
            tmp10 <= "000";
        elsif(CLK‘event and CLK=‘1‘) then
            if(tmp1 = 9) then
                tmp1 <= "0000";
                if(tmp10 = 5) then tmp10 <= "000";
                else tmp10 <= tmp10 + 1;
                end if;
            else tmp1 <= tmp1 + 1;
            end if;
        end if;
    end process;
    s1 <= tmp1;
    s10 <= tmp10;
    c0 <= ‘1‘ when(tmp10 = 5 and tmp1 = 9)
    else ‘0‘;
end art;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity window is
port(
    I:    in std_logic_vector(3 downto 0);
    A:    out std_logic_vector(6 downto 0)
);
end window;

architecture art of window is
begin
    with I select
        A <="1111110" when "0000",
            "0001100" when "0001",
            "1101101" when "0010",
            "1111001" when "0011",
            "0110011" when "0100",
            "1011011" when "0101",
            "0011111" when "0110",
            "1110000" when "0111",
            "1111111" when "1000",
            "1110011" when "1001",
            "0000000" when others;
end art;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity trai is
port(
    I, G : in std_logic;
    Aout: out std_logic
);
end trai;

architecture art of trai is
begin
    process(I,G)
    begin
        if(G = ‘0‘) then Aout <= I;
        else Aout <= ‘Z‘;
        end if;
    end process;
end art;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity prec is
port(
    I:    in std_logic_vector(1 downto 0);
    A:    out std_logic_vector(3 downto 0)
);
end prec;

architecture art of prec is
begin
    with I select
        A <="1110" when "00",
            "1101" when "01",
            "1011" when "10",
            "0111" when others;
end art;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity selecter is
port(
    I, R:    in std_logic_vector(3 downto 0);
    Aout:    out std_logic
);
end selecter;

architecture art of selecter is
begin
    Aout <= R(0) when I = "1110" else
            R(1) when I = "1101" else
            R(2) when I = "1011" else
            R(3) when I = "0111" else
            ‘0‘;
end art;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sour is
port(
    CLK:    in std_logic;
    CLK2:    out std_logic
);
end sour;

architecture art of sour is
    signal tmp : std_logic_vector(9 downto 0);
begin
    process(CLK)
    begin
        if(tmp = 999) then tmp <= "0000000000";
        else tmp <= tmp + 1;
        end if;
    end process;
    CLK2 <= ‘1‘ when tmp = 999 else ‘0‘;
end art;