https://en.wikipedia.org/wiki/Symmetric_multiprocessor_system
A symmetric multiprocessor system (SMP) is a multiprocessor system with centralized shared memory called main memory (MM) operating under a single operating system with two or more homogeneous processors—i.e., it is not a heterogeneous computing system.
More precisely, an SMP is a tightly coupled multiprocessor system with a pool of homogeneous processors running independently, each processor executing different programs and working on different data, with the capability to share resources (memory, I/O device, interrupt system, etc.), and connected using a system bus or a crossbar. An SMP attempts to balance workload across its processors in order to optimize performance. If performance improved with additional processors in a perfectly linear manner, two processors would run twice as fast as one and ten processors would run ten times as fast as a single processor. However, this performance increase is not necessarily linear due to critical sections in the operating system that must be executed serially. This limitation on speedup based on serial sections is represented in Amdahl‘s law.[1][2][3]
Each processor usually has an associated private high-speed memory known as cache memory (or cache) to speed-up the MM data access and to reduce the system bus traffic. These caches store values temporarily that may be accessed by a processor multiple times. This reduces latency by preventing multiple unnecessary memory accesses. A single cache can be used per processor, or multiple levels of cache memory may be employed to further increase efficiency.[3]
According to Flynn‘s taxonomy, a SMP is a type of multiple instruction, multiple data (MIMD) architecture with uniform memory access (UMA) since all processors have the same latency when accessing memory. It is important to note that the term SMP is sometimes loosely used to describe architectures where memory access does not differ by a significant amount (although it may differ somewhat). [4]