//控制字有评估板得到，用此程序时候需要重新计算；
//这个程序只给出了sdata和le的输出值，其他的复位和时钟需要单独给出；
//本人应用时，配置时钟是2MHz（本模块sdata输出速率时钟），ADF4350时钟源时钟是10MHz；
//可以添加跳频功能，需要另外加入else if控制程序；
else if (en == 1‘b0 && set_done == 1‘b0) begin //上电后控制配置，配置完后进入等待状态（set_done拉高）；
case (state)
idle: begin
state <= wr5;
sreg <= 32‘h 00580005;//reg5;
le <= 1‘b0;
cnt <= 6‘d32;
set_done<= 1‘b0;
end
wr5: begin //配置reg5；
if (cnt == 6‘d0) begin //送出32个控制字后，给出le；
le <= 1‘b1; //le拉高，reg5配置完成；
state <= wr4; //下一个状态，reg4；
sreg <= 32‘h 0085003c; //reg4,32位控制字表示成16进制数字；
cnt <= 6‘d32;
end
else begin
cnt <= cnt - 1‘b1;
sreg <= {sreg[30:0],1‘b0};//对控制字进行左移操作；
dout <= sreg[31]; //每次都送出sreg的最高位；
le <= 1‘b0;
end
end
wr4: begin //功能参考wr5;
if (cnt == 6‘d0) begin
le <= 1‘b1;
state <= wr3;
sreg <= 32‘h 000404b3;//reg3;
cnt <= 6‘d32;
end
else begin
cnt <= cnt - 1‘b1;
sreg <= {sreg[30:0],1‘b0};
dout <= sreg[31];
le <= 1‘b0;
end
end
wr3: begin //功能参考wr5;
if (cnt == 6‘d0) begin
le <= 1‘b1;
state <= wr2;
sreg <= 32‘h 1a009fc2;//reg2:digital lock detect
cnt <= 6‘d32;
end
else begin
cnt <= cnt - 1‘b1;
sreg <= {sreg[30:0],1‘b0};
dout <= sreg[31];
le <= 1‘b0;
end
end
wr2: begin //功能参考wr5;
if (cnt == 6‘d0) begin
le <= 1‘b1;
state <= wr1;
sreg <= 32‘h 08008011;//reg1;
cnt <= 6‘d32;
end
else begin
cnt <= cnt - 1‘b1;
sreg <= {sreg[30:0],1‘b0};
dout <= sreg[31];
le <= 1‘b0;
end
end
wr1: begin //功能参考wr5;
if (cnt == 6‘d0) begin
le <= 1‘b1;
state <= wr0;
sreg <= 32‘h 00960000;//reg0;
cnt <= 6‘d32;
end
else begin
cnt <= cnt - 1‘b1;
sreg <= {sreg[30:0],1‘b0};
dout <= sreg[31];
le <= 1‘b0;
end
end
wr0: begin //功能参考wr5;
if (cnt == 6‘d0) begin
le <= 1‘b1;
state <= idle;
cnt <= 6‘d32;
set_done <= 1‘b1; //配置完6个控制字后，set_done拉高，不再进行操作，等待en进行跳频；
end
else begin
cnt <= cnt - 1‘b1;
sreg <= {sreg[30:0],1‘b0};
dout <= sreg[31];
le <= 1‘b0;
end
end
default:begin
le <= 1‘b0;
state <= idle;
sreg <= 32‘h 00960000;
cnt <= 6‘d32;
set_done <= 1‘b0;
end
endcase
end
ADF4350初始化程序（verilog）