1 module move_led
2 (
3 clk,
4 rst,
5 led
6 );
7
8 input clk;
9 input rst;
10
11 output [5:0]led;
12
13 reg [23:0]count;
14 always @(posedge clk or negedge rst)
15 begin
16 if(!rst) count <= 24‘d0;
17 else if(count == 24‘hffffff) count <= 24‘d0;
18 else count <= count + 1‘d1;
19 end
20
21 reg [5:0]led_r;
22 always @(posedge clk or negedge rst)
23 begin
24 if(!rst) led_r <= 6‘b111_110;
25 else if (count == 24‘hfffffe) led_r <= {led_r[4:0],led_r[5]};
26 else led_r <= led_r;
27 end
28
29 assign led = led_r;
30
31 endmodule
时间： 2024-10-25 12:03:07