【黑金教程笔记之002】【建模篇】【Lab 01 永远的流水灯】—笔记&勘误

学习并行操作的思想。

勘误001：

Page 17，模块图下方，“扫描频配置定为100Hz”应为10Hz。

勘误002：

Page 17，最后一行

“10ms”应为100ms；“2.5ms”应为25ms；（ps：这里用1000ms，每个led亮250ms效果比较明显）

源码如下：

 1 /*************************************************
 2 module name:led0_module.v
 3 function:drive led on for 25ms;
 4
 5 by yf.x
 6 2014-11-3
 7 **************************************************/
 8 module led0_module(
 9 CLK,RST_n,LED0
10 );
11
12 input CLK,RST_n;
13 output LED0;
14
15 /****************************************/
16 //DE2-115 has 50MHz oc,so 50M*1s=50_000_000
17 parameter T1000ms=26‘d50_000_000;
18 /****************************************/
19 //1000ms counter
20
21 reg [25:0]count1;
22
23 always @(posedge CLK or negedge RST_n)
24 if(!RST_n)
25   count1<=26‘d0;
26 else if(count1==T1000ms)
27   count1<=26‘d0;
28 else
29   count1<=count1+1‘b1;
30
31 /***************************************/
32 // control led on for 100ms
33
34 reg rLED;
35
36 always @(posedge CLK or negedge RST_n)
37 if(!RST_n)
38   rLED<=1‘b0;
39 else if(count1>=26‘d0 && count1<26‘d1_2500_000)
40   rLED<=1‘b1;
41 else
42   rLED<=1‘b0;
43
44 /***************************************/
45
46 assign LED0=rLED;
47
48 endmodule
49
50
51       

 1 /*************************************************
 2 module name:led1_module.v
 3 function:drive led on for 25ms;
 4
 5 by yf.x
 6 2014-11-3
 7 **************************************************/
 8 module led1_module(
 9 CLK,RST_n,LED1
10 );
11
12 input CLK,RST_n;
13 output LED1;
14
15 /****************************************/
16 //DE2-115 has 50MHz oc,so 50M*1=50_000_000
17 parameter T1000ms=26‘d50_000_000;
18 /****************************************/
19 //1000ms counter
20
21 reg [25:0]count1;
22
23 always @(posedge CLK or negedge RST_n)
24 if(!RST_n)
25   count1<=26‘d0;
26 else if(count1==T1000ms)
27   count1<=26‘d0;
28 else
29   count1<=count1+1‘b1;
30
31 /***************************************/
32 // control led on for 100ms
33
34 reg rLED;
35
36 always @(posedge CLK or negedge RST_n)
37 if(!RST_n)
38   rLED<=1‘b0;
39 else if(count1>=26‘d1_2500_000 && count1<26‘d2_5000_000)
40   rLED<=1‘b1;
41 else
42   rLED<=1‘b0;
43
44 /***************************************/
45
46 assign LED1=rLED;
47
48 endmodule
49
50
51       

 1 /*************************************************
 2 module name:led2_module.v
 3 function:drive led on for 25ms;
 4
 5 by yf.x
 6 2014-11-3
 7 **************************************************/
 8 module led2_module(
 9 CLK,RST_n,LED2
10 );
11
12 input CLK,RST_n;
13 output LED2;
14
15 /****************************************/
16 //DE2-115 has 50MHz oc,so 50M*1=50_000_000
17 parameter T1000ms=26‘d50_000_000;
18 /****************************************/
19 //1000ms counter
20
21 reg [25:0]count1;
22
23 always @(posedge CLK or negedge RST_n)
24 if(!RST_n)
25   count1<=26‘d0;
26 else if(count1==T1000ms)
27   count1<=26‘d0;
28 else
29   count1<=count1+1‘b1;
30
31 /***************************************/
32 // control led on for 100ms
33
34 reg rLED;
35
36 always @(posedge CLK or negedge RST_n)
37 if(!RST_n)
38   rLED<=1‘b0;
39 else if(count1>=26‘d2_5000_000 && count1<26‘d3_7500_000)
40   rLED<=1‘b1;
41 else
42   rLED<=1‘b0;
43
44 /***************************************/
45
46 assign LED2=rLED;
47
48 endmodule
49
50
51       

 1 /*************************************************
 2 module name:led3_module.v
 3 function:drive led on for 25ms;
 4
 5 by yf.x
 6 2014-11-3
 7 **************************************************/
 8 module led3_module(
 9 CLK,RST_n,LED3
10 );
11
12 input CLK,RST_n;
13 output LED3;
14
15 /****************************************/
16 //DE2-115 has 50MHz oc,so 50M*1=50_000_000
17 parameter T1000ms=26‘d50_000_000;
18 /****************************************/
19 //1000ms counter
20
21 reg [25:0]count1;
22
23 always @(posedge CLK or negedge RST_n)
24 if(!RST_n)
25   count1<=26‘d0;
26 else if(count1==T1000ms)
27   count1<=26‘d0;
28 else
29   count1<=count1+1‘b1;
30
31 /***************************************/
32 // control led on for 100ms
33
34 reg rLED;
35
36 always @(posedge CLK or negedge RST_n)
37 if(!RST_n)
38   rLED<=1‘b0;
39 else if(count1>=26‘d3_7500_000 && count1<26‘d50_000_000)
40   rLED<=1‘b1;
41 else
42   rLED<=1‘b0;
43
44 /***************************************/
45
46 assign LED3=rLED;
47
48 endmodule
49
50
51       

 1 /*********************************
 2 module name:top.v
 3 function:control 4 led on for 250ms
 4 (for DE2-115)
 5 pin assignments:
 6 ---------------------------------
 7 CLK----------------------CLOCK_50
 8 RST_n--------------------KEY[0]
 9 LED(0-3)-----------------LEDG[0-3]
10 ---------------------------------
11
12 yf.x
13 2014-11-03
14 **********************************/
15
16 module top(
17 CLK,RST_n,LED
18 );
19
20 input CLK,RST_n;
21 output [3:0]LED;
22
23 /*********************************/
24
25 wire [3:0]LED_out;
26
27 led0_module u0(
28 .CLK(CLK),
29 .RST_n(RST_n),
30 .LED0(LED_out[0])
31 );
32
33 /*********************************/
34
35 led1_module u1(
36 .CLK(CLK),
37 .RST_n(RST_n),
38 .LED1(LED_out[1])
39 );
40
41 /*********************************/
42
43 led2_module u2(
44 .CLK(CLK),
45 .RST_n(RST_n),
46 .LED2(LED_out[2])
47 );
48
49 /*********************************/
50
51 led3_module u3(
52 .CLK(CLK),
53 .RST_n(RST_n),
54 .LED3(LED_out[3])
55 );
56
57 /*********************************/
58
59 assign LED=LED_out;
60
61 endmodule