使用tcl文件分配管脚

之前在进行简单的设计的时候，分配管脚比较少，就用的pin planner一个一个输入。现在在做一个大的系统，这样做就太麻烦，在网上搜到了用tcl文件分配管脚的方法。

步骤如下：

首先生成tcl文件，具体做法是project--Generate Tcl Files for project，注意不要勾选include default assignments选项，第一次勾选了之后，提示错误。

然后在文件中间按照下面的格式对管脚进行分配即可。

set_location_assignment PIN_N8 -to RESET

生成的Tcl文件如下，#相当于注释的作用：

# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation‘s design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.

# Quartus II: Generate Tcl File for Project
# File: DAQ.tcl
# Generated on: Fri Feb 26 15:12:54 2016

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
    if {[string compare $quartus(project) "DAQ"]} {
        puts "Project DAQ is not open"
        set make_assignments 0
    }
} else {
    # Only open if not already open
    if {[project_exists DAQ]} {
        project_open -revision DAQ DAQ
    } else {
        project_new -revision DAQ DAQ
    }
    set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
    set_global_assignment -name FAMILY "Cyclone IV E"
    set_global_assignment -name DEVICE EP4CE10F17C8
    set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
    set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:35  FEBRUARY 23, 2016"
    set_global_assignment -name LAST_QUARTUS_VERSION 13.0
    set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
    set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
    set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
    set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
    set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
    set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
    set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
    set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
    set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
    set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
    set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
    set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
    set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
    set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
    set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
    set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
    set_global_assignment -name QSYS_FILE Qsys_files/HardCore.qsys
    set_global_assignment -name QIP_FILE PLL.qip
    set_global_assignment -name BDF_FILE DAQ.bdf
    set_global_assignment -name VERILOG_FILE AD_conv.v
    set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

    set_location_assignment PIN_N8 -to RESET
    set_location_assignment PIN_E1 -to SYS_CLK

    #SDRAM
    set_location_assignment PIN_A14 -to SdramClk    

    set_location_assignment PIN_D5 -to DQ[0]
    set_location_assignment PIN_B5 -to DQ[1]
    set_location_assignment PIN_D6 -to DQ[2]
    set_location_assignment PIN_C6 -to DQ[3]
    set_location_assignment PIN_B6 -to DQ[4]
    set_location_assignment PIN_B7 -to DQ[5]
    set_location_assignment PIN_D8 -to DQ[6]
    set_location_assignment PIN_C8 -to DQ[7]
    set_location_assignment PIN_A9 -to DQ[8]
    set_location_assignment PIN_A8 -to DQ[9]
    set_location_assignment PIN_A7 -to DQ[10]
    set_location_assignment PIN_A6 -to DQ[11]
    set_location_assignment PIN_A5 -to DQ[12]
    set_location_assignment PIN_A4 -to DQ[13]
    set_location_assignment PIN_A3 -to DQ[14]
    set_location_assignment PIN_A2 -to DQ[15]

    set_location_assignment PIN_B11 -to ADDR[0]
    set_location_assignment PIN_D12 -to ADDR[1]
    set_location_assignment PIN_B12 -to ADDR[2]
    set_location_assignment PIN_B13 -to ADDR[3]
    set_location_assignment PIN_C16 -to ADDR[4]
    set_location_assignment PIN_B16 -to ADDR[5]
    set_location_assignment PIN_C15 -to ADDR[6]
    set_location_assignment PIN_A15 -to ADDR[7]
    set_location_assignment PIN_B14 -to ADDR[8]
    set_location_assignment PIN_C14 -to ADDR[9]
    set_location_assignment PIN_C11 -to ADDR[10]
    set_location_assignment PIN_A13 -to ADDR[11]
    set_location_assignment PIN_A12 -to ADDR[12]

    set_location_assignment PIN_B10 -to BA[0]
    set_location_assignment PIN_D11 -to BA[1]

    set_location_assignment PIN_B8 -to DQM[0]
    set_location_assignment PIN_A10 -to DQM[1]

    set_location_assignment PIN_A11 -to CKE
    set_location_assignment PIN_D9 -to nCAS
    set_location_assignment PIN_B9 -to nCS
    set_location_assignment PIN_C9 -to nRAS
    set_location_assignment PIN_E9 -to nWE

    #FLASH

    set_location_assignment PIN_H1 -to DCLK_EPCS
    set_location_assignment PIN_D2 -to SCE_EPCS
    set_location_assignment PIN_C1 -to SDO_EPCS
    set_location_assignment PIN_H2 -to DATA0_EPCS

    # Close project
    if {$need_to_close_project} {
        project_close
    }
}

然后加载tcl文件，对bdf文件分配管脚，具体操作如下：

tools--Tcl scripts,弹出对话框，选择要加载的tcl文件，点击Run即可。