FPGA入门——basys2开发板的伪随机gold码的生成

本文原创，转载请注明出处。

1.gold码简介

gold码是一种伪随机码，由两个m序列通过不同的相位抽头与或产生，具有很好的自相关与互相关特性，广泛应用于扩频通信。GPS中使用的C/A扩频码即10位寄存器长度的gold码。

2.设计目标

本文在basys2内部产生10位寄存器长度的gold码，通过开关控制相位抽头，并通过0.5s刷新速度的LED流水灯显示。

3.vhdl源码

  1 library IEEE;
  2 use IEEE.STD_LOGIC_1164.ALL;
  3 use IEEE.STD_LOGIC_ARITH.ALL;
  4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5
  6 entity top is
  7     port(
  8             clk        :    in        STD_LOGIC;    --系统时钟
  9             rst        :    in     STD_LOGIC;    --reset
 10             tap_1        :    in        STD_LOGIC_VECTOR ( 3 downto 0 );    --m序列相位选择，根据具体输入硬件而定
 11             tap_2        :    in        STD_LOGIC_VECTOR ( 3 downto 0 );
 12             led        :    out    STD_LOGIC_VECTOR ( 7 downto 0 )    --led流水灯控制，根据具体输出硬件而定
 13             );
 14 end top;
 15
 16 architecture Behavioral of top is
 17     signal    reg_1        :    STD_LOGIC_VECTOR( 9 downto 0 );    --10位循环移位寄存器
 18     signal    reg_2        :    STD_LOGIC_VECTOR( 9 downto 0 );
 19     signal    reg_gold    :    STD_LOGIC_VECTOR( 7 downto 0 );    --gold码8位缓存用于显示
 20     signal    tmp_1        :    STD_LOGIC;    --循环移位反馈信号
 21     signal    tmp_2        :    STD_LOGIC;
 22     signal    m_1        :    STD_LOGIC;    --m序列
 23     signal    m_2        :    STD_LOGIC;
 24     signal    gold        :    STD_LOGIC;    --gold序列
 25     signal    clk_sec    :    STD_LOGIC:=‘0‘;    --秒时钟
 26     signal    cnt_sec    :    INTEGER;    --用于产生秒时钟的模
 27
 28 begin
 29 led(7 downto 0)<=reg_gold(7 downto 0);    --输出给8个Led灯
 30
 31     --产生秒时钟clk_sec的模块
 32     process(clk,rst)
 33     begin
 34     if (rst=‘0‘) then
 35         cnt_sec<=0;
 36     elsif(clk‘event and clk=‘1‘) then
 37         if(cnt_sec=12500000) then
 38             cnt_sec<=0;
 39             clk_sec<=not clk_sec;
 40         else
 41             cnt_sec<=cnt_sec+1;
 42         end if;
 43     end if;
 44     end process;
 45
 46     --产生m序列1
 47     process(clk_sec,rst,reg_1)
 48     begin
 49     tmp_1<=reg_1(2) xor reg_1(9);    --反馈抽头在第3、10位
 50         if (rst=‘0‘) then
 51             reg_1<=(others=>‘1‘);
 52         elsif (clk_sec‘event and clk_sec=‘1‘) then
 53             reg_1<=reg_1(8 downto 0)&tmp_1;    --循环移位
 54         end if;
 55     end process;
 56
 57     --产生m序列2
 58     process(clk_sec,rst,reg_2)
 59     begin
 60     tmp_2<=(reg_2(1) xor reg_2(2))xor(reg_2(7) xor reg_2(9));    --反馈抽头在2、3、8、10位
 61         if (rst=‘0‘) then
 62             reg_2<=(others=>‘1‘);
 63         elsif (clk_sec‘event and clk_sec=‘1‘) then
 64             reg_2<=reg_2(8 downto 0)&tmp_2;    --循环移位
 65         end if;
 66     end process;
 67
 68     --m序列1的相位抽头选择，本部分根据具体输入硬件编程
 69     process(tap_1,reg_1)
 70     begin
 71         case tap_1 is
 72             when    b"0001"=>m_1<=reg_1(1);
 73             when    b"0010"=>m_1<=reg_1(2);
 74             when    b"0011"=>m_1<=reg_1(3);
 75             when    b"0100"=>m_1<=reg_1(4);
 76             when    b"0101"=>m_1<=reg_1(5);
 77             when    b"0110"=>m_1<=reg_1(6);
 78             when    b"0111"=>m_1<=reg_1(7);
 79             when    b"1000"=>m_1<=reg_1(8);
 80             when    b"1001"=>m_1<=reg_1(9);
 81             when    others =>m_1<=reg_1(0);
 82         end case;
 83     end process;
 84
 85     --m序列2的相位抽头选择，本部分根据具体输入硬件编程
 86     process(tap_2,reg_2)
 87     begin
 88         case tap_2 is
 89             when    b"0001"=>m_2<=reg_2(1);
 90             when    b"0010"=>m_2<=reg_2(2);
 91             when    b"0011"=>m_2<=reg_2(3);
 92             when    b"0100"=>m_2<=reg_2(4);
 93             when    b"0101"=>m_2<=reg_2(5);
 94             when    b"0110"=>m_2<=reg_2(6);
 95             when    b"0111"=>m_2<=reg_2(7);
 96             when    b"1000"=>m_2<=reg_2(8);
 97             when    b"1001"=>m_2<=reg_2(9);
 98             when    others =>m_2<=reg_2(0);
 99         end case;
100     end process;
101
102     --gold码生成
103     process(clk_sec,rst,m_1,m_2)
104     begin
105     gold<=m_1 xor m_2;
106         if (rst=‘0‘) then
107             reg_gold<=(others=>‘0‘);
108         elsif (clk_sec‘event and clk_sec=‘1‘) then
109             reg_gold<=reg_gold(6 downto 0)&gold;
110         end if;
111     end process;
112
113 end Behavioral;

4.引脚定义

 1 NET    "clk"             LOC="B8";
 2 NET    "rst"             LOC="G12";
 3 NET    "tap_1<0>"        LOC="N3";
 4 NET    "tap_1<1>"        LOC="E2";
 5 NET    "tap_1<2>"        LOC="F3";
 6 NET    "tap_1<3>"        LOC="G3";
 7 NET    "tap_2<0>"        LOC="B4";
 8 NET    "tap_2<1>"        LOC="K3";
 9 NET    "tap_2<2>"        LOC="L3";
10 NET    "tap_2<3>"        LOC="P11";
11 NET    "led<0>"          LOC="M5";
12 NET    "led<1>"          LOC="M11";
13 NET    "led<2>"          LOC="P7";
14 NET    "led<3>"          LOC="P6";
15 NET    "led<4>"          LOC="N5";
16 NET    "led<5>"          LOC="N4";
17 NET    "led<6>"          LOC="P4";
18 NET    "led<7>"          LOC="G1";