Transistor latch improves on/off circuitry

Figure 1 shows an example of on/off circuitry commonly used in battery-operated devices. The p-channel MOSFET, Q1, serves as a power switch. When you push the On button, S1, Q1‘s gate goes low. Q1 turns on and supplies battery voltage to the dc/dc converter. Depending on the battery voltage in the device, the dc/dc converter might convert the voltage either up or down. In either case, it supplies VCC to the µC. The µC goes through its power-up software sequence and programs one of its general-purpose I/O pins, setting it to logic one. This operation, in turn, causes saturation of the npn transistor, Q2, which "confirms" the power-up state. Later, when the µC decides to power itself off, the µC simply sets its I/O output to logic zero, and Q1returns to its off state. The circuit is simple and reliable but has a significant disadvantage. It usually takes a fraction of a second for the dc/dc converter to reach its stable output voltage. Then, the µC‘s Reset pulse usually lasts 50 to 200 msec. After the release of Reset, the µC must go through its "housekeeping" start-up code before it has a chance to set its I/O pin to logic one. This delay in some portable systems may be user-unfriendly, because if you don‘t depress the On button long enough, the system will not power up. The circuit in Figure 2 eliminates this uncertainty.

The circuit includes a simple two-transistor latch, which the On button switches to the on state. As in Figure 1, the p-channel MOSFET, Q1, serves as a power switch. When you push the On button, S1, it causes saturation of the npn transistor, Q4, via the base-current-limiting resistor, R5. The collector current of Q4 flows through R1 and the base-emitter junction of pnp transistor Q3, thereby saturating Q3. Q3 redirects some current into the base-emitter junction of Q4 and finishes the latching process. At this point, both Q3 and Q4 are saturated, and the voltage on the gate of Q1 is a function of the voltage drop across the base-emitter junction of Q3 and the saturation voltage of Q4. This voltage is approximately 0.9V. The µC need not confirm the on state of the latch. When the µC powers up and finishes its housekeeping start-up code, it programs the I/O pin to logic zero.

Later, when the µC decides to power itself off, it programs the I/O pin to logic one and stops. Q2 turns off Q4, resetting the latch to its initial off state. R4 lowers the equivalent input impedance of Q3. This function improves EMI and ESD noise immunity and prevents the circuit from turning itself on in the presence of strong electromagnetic fields. Capacitor C1 in combination with R5 protects Q4 and Q2 from direct ESD into the pushbutton. Some portable devices use undervoltage-lockout circuitry. This circuitry usually uses a voltage comparator with a built-in voltage reference. If the battery voltage drops below the threshold, the output of the comparator (usually an open-drain type) switches low. If your portable system uses this type of circuitry, you can connect the open-drain output of the comparator in parallel with Q2, thus preventing the latch from turning on if the battery voltage is too low.

时间: 2024-10-08 20:05:25

Transistor latch improves on/off circuitry的相关文章

RFID Exploration and Spoofer a bipolar transistor, a pair of FETs, and a rectifying full-bridge followed by a loading FET

RFID Exploration Louis Yi, Mary Ruthven, Kevin O'Toole, & Jay Patterson What did you do? We made an Radio Frequency ID (RFID) card reader and, while attempting to create a long-range spoofer, created an jammer which overcomes card's signals. The read

PatentTips - Integrated circuit well bias circuitry

1. Field of the Invention This invention relates in general to an integrated circuit and more specifically to well biasing circuitry for transistors of an integrated circuit. 2. Description of the Related Art Integrated circuits utilize transistors,

Transistor 晶体管 场效应 双极型 达林顿 CMOS PMOS BJT FET

Transistor Tutorial Summary Transistor Tutorial Summary Bipolar Junction Transistor Tutorial We can summarise this transistors tutorial section as follows: The Bipolar Junction Transistor (BJT) is a three layer device constructed form two semiconduct

Inverted bipolar transistor doubles as a signal clamp

A number of circuits, such as level detectors and AM demodulators, benefit from a rectifier with a low offset voltage. Silicon diodes have an offset of approximately 0.6V and do not work well in low-level circuitry. A Schottky diode is a bit better w

关于MySQL latch争用深入分析与判断

1.latch锁是什么锁? 2.latch锁是如何保护list? 3.latch争用的现象和过程? 4.latch什么时候会产生严重的争用? 5.如何监控latch争用情况? 6.如何确认latch争用类型? 7.如何降低latch争用? 一.latch锁是什么锁 1.定义 latch锁是内存锁,是一个小型的在内存中保护list的内存锁结构. 2.特点 1.不排队 2.spin,一个线程想获得一个锁,但是该锁已被另一线程持有,进行spin(空转随机时间)占用cpu间接性的等待锁的释放,然后获取去

手动模拟获取latch

随意dump一个latches结构文件: SQL> oradebug dump latches 10 ORA-00074: no process has been specified SQL> oradebug setmypid Statement processed. SQL> oradebug dump latches 10 Statement processed. SQL> oradebug tracefile_name /oracle/diag/rdbms/orcl/orc

相克军_Oracle体系_随堂笔记014-锁 latch,lock

1.Oracle锁类型     锁的作用     latch锁:chain,链     LOCK锁         排他锁(X)         共享锁(S) 2.行级锁:DML语句     事务锁TX         锁的结构         事务锁的加锁和解锁过程     只有排他锁         不影响读(CR块) 3.表级锁:TM     行级排他锁(Row exclusive)RX锁         当我们进行DML时,会自动在被更新的表上添加RX锁,可以执行LOCK命令显式的在表上

SR latch D latch D filp-flop SR触发器 D触发器 D双稳态多谐震荡器 【数字电路】

SR  latch D latch D filp-flop SR Latch 典型的SR 触发器就长上面那样啦 不要以为简单,酒吧 S R Q Q' 之间的相对位置关系记错了! 组成的元素很简单--或非门,但是实现的功能却很重要 SR是两个输入端口,Q 和 Q' 是输出端口 不要慌,两个端口,就四种输入情况,一个个分析,就可以了解SR latch是怎么工作的 当 s == 1 , R == 0, 或门,只要是有1 ,或门处理结果就是1. 这里S端口输入的是1,那么Q' 得到的是0,这个0反馈到R

[整理]一个有关Latch(锁存器)的有趣问题

起源 今天诳论坛,突然发现了一个有关latch的问题,由于对D Flip-Flop和Latch还有些疑问,就点击了进去,一看果然有些意思,也挺有学习意义的,于是本文就诞生了.喊出口号~Just note it. 有意思的问题图 两个问题. 上面左边描述的电路,如果不加else q<=0;,会生成latch吗? 上面右边描述的电路,如果不加else q<=0;,会生成latch吗? 集思广益 论坛上还是有很多的大神和前辈的,几个回答相当不错,有着极强指导意义,让人不禁思考问题,然后开始默默思考人