module bbbb(clock,oo,ii); input clock; output [4:0]oo; output [4:0]ii; reg [4:0]ooo; reg [4:0]iii; [email protected](posedge clock) begin if(ooo>=16) begin ooo<=0; iii<=iii+1; if(iii>=16) iii<=0; end else ooo<=ooo+1; end assign oo=ooo; assign ii=iii; endmodule
以上的代码仿真的时候会出现STX状态,在网上找到一个说法是程序中应该要有一个RST复位,即
module bbbb(clock,oo,ii,rst); input clock; input rst; output [4:0]oo; output [4:0]ii; reg [4:0]ooo; reg [4:0]iii; [email protected](posedge clock) begin if(!rst)begin ooo<=0;iii<=0;end else begin if(ooo>=16) begin ooo<=0; iii<=iii+1; if(iii>=16) iii<=0; end else ooo<=ooo+1; end end assign oo=ooo; assign ii=iii; endmodule
在仿真激励中应该使rst拉低几个时间,后再写操作
module bbbb_tb ; reg clock ; reg rst ; wire [4:0] ii ; wire [4:0] oo ; bbbb DUT ( .clock (clock ) , .rst (rst ) , .ii (ii ) , .oo (oo ) ); initial begin clock=0; #5 rst=0; #6 rst=1; forever #6 clock=~clock; end endmodule
如上!
时间: 2024-10-13 11:43:30