CSCI 2121: Computer Organization and
Assembly Language
Lab 5
Design Sequential Circuits in Verilog III
February 27, 2019
1 Learning Objectives
In this lab, you will use what we have learned about sequential circuits to implement different
types of shift registers, a sequence detector, and rising edge detectors.
2 Submission Instruction
Save code for each task as .sv file, with the name specified at the end of each lab task.
Put all lab files into one folder, and compress the folder to a .zip file.
Submit it on Brightspace.
Deadline for submission: Sunday 2nd March, 2019, 11:55 pm.
As the marking will be done automatically by a script, it is important that you follow these
instructions and save your files with correct names and .sv extension.
1
3 Lab Assignment
3.1 Lab Task 1
Design a 4-bit shift-left register
Implement a 4-bit shift-left register. The skeleton code is available at
https://www.edaplayground.com/x/34QM. Name your file as task1.sv
Figure 1: 4-bit shift-left register
3.2 Lab Task 2
Design a 4-bit shift-left-or-right register
Implement a 4-bit shift-left-or-right register. It performs the work of the shift right register if
the direction is 0, or the shift left register if the direction is 1. The skeleton code is available here
at https://www.edaplayground.com/x/4C3Z. Name your file as task2.sv
Figure 2: 4-bit shift-left-or-right register
2
3.3 Lab Task 3
CSCI 2121作业代写
Design a 16-bit shift register
Implement a 16-bit shift register using only 4-bit shift-right registers.Complete the circuit and
make sure it passes all tests. The skeleton code is available at https://www.edaplayground.com/x/35JE.
Name your file as task3.sv
3.4 Lab Task 4
Design a sequence detector
Design a finite state machine that has one input line x and one output line z. The input line
receives a stream of bits. The machine outputs a 1 when exactly two of the last three inputs are
1; otherwise, it outputs a zero. An example is shown by Figure 3. The skeleton code is available
at https://www.edaplayground.com/x/3b8Q. Save this file as task4.sv
Figure 3: Sequence detector
3.5 Lab Task 5
Design a rising edge detector (Moore machine)
Figure 4: Rising edge detector (Moore machine)
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原文地址：https://www.cnblogs.com/welhoa/p/10462616.html