在编写Verilog代码时注意以下点：
1 、同一个模块中不同变量的赋值放在不同的always块里（这样可以便于程序的调试），一个always块的代码
尽量不要超过十行。
2、同一个变量的赋值不能放在多个always块中，只能放在同一always块
2、复位信号一定要干净，尽量不要与其他的信号进行逻辑运算
3、利用时钟信号（clk）和复位信号(rst)做触发，尽量避免用中间变量的上升或者下降沿触发
示例代码如下（PN序列的产生）：
//---------------------------------------------------------------------------------------------------
//-- Project name : DTMB 1.0 IP Development
//-- Filename : dtmb_pn_gen.v
//-- Called by : dtmb_pn_gen.v
//-- Description : DTMB fine channle estimation
//-- Moficiation History :
//-------------------------------------------------------------------------------------------
//-- Date | By | Version | Change Description
//-------------------------------------------------------------------------------------------
//-- 2014-07-24 | Zhenzhen Peng | 0.2 | Second Version
//----------------------------------------------------------------------------------------------
`timescale 1ns/10fs
modulepn_module2_m_function
(
// input
i_clk_x16g , // x16 clock, Gated 120.96MHz
i_rst_n , // Negative reset for all EQ
i_m_intiphase , // Initial phase
i_pn_mode , // 0->255, 1->1023, 2->511, 3->x
i_pn_length , // 0->420, 1->595, 2->945, 3->x
i_module2_start , // PN start signal
o_pn_gen_en , // PN seq out enable
o_pn_gen_start , // PN start signal
o_pn_gen_seq , // PN sequence: 0->+PN , 1->-PN
o_module2_count // control the output signal
);
//=========================================================
// Parameter
//=========================================================
parameter D_W = 12,
output_lenght=2048 ; // output data lenght
//=========================================================
// Interface definition
//=========================================================
input i_clk_x16g ; // x16 clock, Gated 120.96MHz
input i_rst_n ;
// Negative reset for all EQ
input [ 1 : 0] i_pn_mode ;
// 0->420, 1->595, 2->945, 3->x
input [ 9 : 0] i_m_intiphase ;
// the PN initial phase
input i_module2_start ; // pn_module2_m_function module start signal
input [ 9 : 0] i_pn_length ;
// 0->420, 1->595, 2->945, 3->x
// output
output o_pn_gen_start ; // PN start signal
output o_pn_gen_en ;
// PN seq out enable
output [D_W-1 : 0] o_pn_gen_seq ;
// PN sequence: 0->+PN , 1->-PN
output [ 11 : 0] o_module2_count ; // control the output signal
//=========================================================
// Behavior
//=========================================================
reg o_pn_gen_start ;
reg o_pn_gen_en ; // PN seq out enable
reg signed [D_W-1 : 0] o_pn_gen_seq ; // PN sequence: 0->+PN , 1->-PN
reg [ 11 : 0] o_module2_count ; // control the output signal of o_m_out,o_module2_over
reg m_flag ;
// m_flag=1, the shifting register is working
reg m_out ; // the output bit value
reg [ 9 : 0] m_Init ; // shifting register
// m_flag
always @(posedge i_clk_x16g or negedge i_rst_n)
//a clk delay use to delivery the phase
begin
if(!i_rst_n) m_flag<=0;
else if(i_module2_start) m_flag<=1;
else m_flag<=0;
end
// o_module2_count
always @(posedge i_clk_x16g
or negedge i_rst_n)
begin
if(!i_rst_n) o_module2_count<=0;
else if (m_flag )o_module2_count<=o_module2_count+1;
else o_module2_count<=0;
end
// o_pn_gen_start
always @(posedge i_clk_x16g
or negedge i_rst_n)
begin
if(!i_rst_n) o_pn_gen_start <=0;
else if(m_flag) begin
if(o_module2_count==1) o_pn_gen_start <=1;
else o_pn_gen_start <=0;
end
end
//o_pn_gen_en
always @(posedge i_clk_x16g
or negedge i_rst_n)
begin
if(!i_rst_n) o_pn_gen_en <=0;
else if(m_flag) begin
if(o_module2_count==1)o_pn_gen_en <=1;
if(o_module2_count==output_lenght+1)o_pn_gen_en <=0;
end
end
//o_pn_gen_seq
always @(posedge i_clk_x16g or negedge i_rst_n)
begin
if(!i_rst_n) o_pn_gen_seq<=0;
else if(o_module2_count) // output_lenght 2048
if(o_module2_count<=i_pn_length)
begin
if(m_out==1) o_pn_gen_seq<=-362; //BPSK mapper: 1—> -1 0—>1 then QPSK mapper:(sqrt(2)/2 )*(1+i),and(12,2,t)quantitative,
so is 362
//the Real data is similar to the imaginary data
else
o_pn_gen_seq<=362;
end
else o_pn_gen_seq<=0;
end
//m_Init
//m_out
always @(posedge i_clk_x16g
or negedge i_rst_n)
begin
if(!i_rst_n)begin
m_Init<=0;
m_out<=0;
end
else begin
//m sequence generator
if(!m_flag && i_module2_start) m_Init<=i_m_intiphase;
else if(o_module2_count<=i_pn_length)
case(i_pn_mode)//0->PN420, 1->PN595, 2->PN945
2‘b00: begin //255
m_out <=m_Init[7];
m_Init<= {m_Init[6:0],m_Init[7]^m_Init[5]^m_Init[4]^m_Init[0]};
end
2‘b01: begin
//1023
m_out <=m_Init[9];
m_Init <= {m_Init[8:0],m_Init[9]^m_Init[2]};
end
2‘b10: begin//511
m_out <=m_Init[8];
m_Init <= {m_Init[7:0],m_Init[8]^m_Init[7]^m_Init[6]^m_Init[1]};
end
endcase
end
end
endmodule
verilog代码风格——PN序列产生代码