Zynq ZC702平台 QSPI + eMMC实现

预备知识:

UG821

The processor system boot is a two-stage process:

? Another boot mode supported through FSBL is eMMC boot mode. This boot mode is possible only when the primary boot mode (set through the boot mode pins) is QSPI.
This is used when you have a small QSPI flash and would like to store all the other partitions on a larger flash memory like eMMC. In this case, place the FSBL on the QSPI flash, and all the other partitions on eMMC flash.

指导步骤:

To enable and use this boot mode:
1. Create a BSP with the library and set enable_mmc in the SDK options. For more details, see the library documentation.
2. Enable the MMC_SUPPORT flag through SDK and build FSBL. The FSBL image build (fsbl.elf) now has eMMC support.
3. Stitch the boot image with FSBL as the only partition (using Bootgen).
4. Place the boot image in the QSPI flash.
5. Stitch an image (using Bootgen) with all the other required partitions (like the bitstream or the U-Boot) and place it in the eMMC.
6. Set the boot mode to QSPI.
7. Power cycle the board.

具体实现:

Step1. Create a BSP with the library and set enable_mmc in the SDK options. For more details, see the library documentation.

--建立FSBL,点击 Modify this BSP‘s Settings --> Supported Libaries中选中xilffs

--xilffs的pdf见《UG1032》

Step2:Enable the MMC_SUPPORT flag through SDK and build FSBL. The FSBL image build (fsbl.elf) now has eMMC support.

--FSBL工程,右键,弹出菜单中选中 C/C++ Building Settings 添加 -DMMC_SUPPORT

Step3.  Stitch the boot image with FSBL as the only partition (using Bootgen).

--SDK下用Bootgen只添加FSBL,生成BOOT.BIN,

Step4. Place the boot image in the QSPI flash.

--通过JTAG烧录step3中生产的BOOT.BIN文件到QSPI中

Step5. Stitch an image (using Bootgen) with all the other required partitions (like the bitstream or the U-Boot) and place it in the eMMC.

--SDK下用Bootgen添加bitstream or the U-Boot,生成BOOT.BIN, 这个文件要拷贝到eMMC中

Step6. 拷贝step5生产的BOOT.bin,以及uImage,devicetree,ramdisk到SD中,启动

--由于ZC702没有eMMC,用SD代理,原理一样,

--量产时eMMC用烧录器烧写

以下是log

U-Boot 2016.07 (Dec 12 2016 - 23:04:43 -0700)

Model: Zynq ZC702 Development Board
Board: Xilinx Zynq
I2C:   ready
DRAM:  ECC disabled 1 GiB
MMC:   [email protected]: 0
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB
In:    [email protected]
Out:   [email protected]
Err:   [email protected]
Model: Zynq ZC702 Development Board
Board: Xilinx Zynq
Net:   ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
eth0: [email protected]
Hit any key to stop autoboot:  0
Copying Linux from QSPI flash to RAM...
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB
device 0 offset 0x100000, size 0x500000
SF: 5242880 bytes @ 0x100000 Read: OK
device 0 offset 0x600000, size 0x20000
SF: 131072 bytes @ 0x600000 Read: OK
Copying ramdisk...
device 0 offset 0x620000, size 0x8f0000
SF: 9371648 bytes @ 0x620000 Read: OK
## Booting kernel from Legacy Image at 02080000 ...
   Image Name:   Linux-4.9.0-xilinx
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    3756496 Bytes = 3.6 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 04000000 ...
   Image Name:   petalinux-minimal-zc702-zynq7-20
   Image Type:   ARM Linux RAMDisk Image (gzip compressed)
   Data Size:    8487267 Bytes = 8.1 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 02000000
   Booting using the fdt blob at 0x2000000
   Loading Kernel Image ... OK
   Loading Ramdisk to 1f7e7000, end 1ffff163 ... OK
   Loading Device Tree to 1f7e0000, end 1f7e694e ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.9.0-xilinx ([email protected]) (gcc version 4.9.2 (Sourcery CodeBench Lite 2015.05-17) ) #3 SMP PREEMPT Fri Aug 25 07:42:38 HKT 2017
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt:Machine model: Zynq ZC702 Development Board
cma: Reserved 16 MiB at 0x3f000000
Memory policy: Data cache writealloc
percpu: Embedded 14 pages/cpu @ef7ce000 s25984 r8192 d23168 u57344
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260608
Kernel command line:
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1005028K/1048576K available (6144K kernel code, 201K rwdata, 1448K rodata, 1024K init, 230K bss, 27164K reserved, 16384K cma-reserved, 245760K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc0700000   (7136 kB)
      .init : 0xc0900000 - 0xc0a00000   (1024 kB)
      .data : 0xc0a00000 - 0xc0a32680   ( 202 kB)
       .bss : 0xc0a32680 - 0xc0a6c09c   ( 231 kB)
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
efuse mapped to f0800000
slcr mapped to f0802000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at f0802100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at f080a000, irq=17
Console: colour dummy device 80x30
console [tty0] enabled
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100058
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
zynq-gpio e000a000.gpio: could not find pctldev for node /amba/[email protected]/[email protected]/gpio0-default, deferring probe
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: can‘t request region for resource [mem 0xfffc0000-0xffffffff]
zynq-ocm: probe of f800c000.ocmc failed with error -16
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
Freeing initrd memory: 8292K (df7e7000 - e0000000)
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
workingset: timestamp_bits=30 max_order=18 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY)  ?? 2001-2006 Red Hat, Inc.
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 27, base_baud = 3125000) is a xuartps
console [ttyPS0] enabled
[drm] Initialized
brd: module loaded
loop: module loaded
libphy: Fixed MDIO Bus: probed
CAN device driver interface
libphy: MACB_mii_bus: probed
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 29 (00:0a:35:00:01:22)
Marvell 88E1116R e000b000.etherne:07: attached PHY driver [Marvell 88E1116R] (mii_bus:phy_addr=e000b000.etherne:07, irq=-1)
e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 ‘Enhanced‘ Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
e0002000.usb supply vbus not found, using dummy regulator
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 24
si570 1-005d: registered, current frequency 148500000 Hz
i2c i2c-0: Added multiplexed i2c bus 1
i2c i2c-0: Added multiplexed i2c bus 2
at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
i2c i2c-0: Added multiplexed i2c bus 3
i2c i2c-0: Added multiplexed i2c bus 4
rtc rtc0: invalid alarm value: 2017-10-12 44:23:0
rtc-pcf8563 5-0051: rtc core: registered rtc-pcf8563 as rtc0
i2c i2c-0: Added multiplexed i2c bus 5
i2c i2c-0: Added multiplexed i2c bus 6
i2c i2c-0: Added multiplexed i2c bus 7
i2c i2c-0: Added multiplexed i2c bus 8
pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
ucd9200 8-0034: Device ID UCD9248-80|5.8.0.11400|091112
ucd9200 8-0034: 4 rails configured
random: fast init done
ucd9200 8-0035: Device ID UCD9248-80|5.8.0.11400|091112
ucd9200 8-0035: 4 rails configured
ucd9200 8-0036: Device ID UCD9248-80|5.8.0.11400|091112
ucd9200 8-0036: 2 rails configured
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using DMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered protocol family 10
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20161123 t)
can: netlink gateway (rev 20130117) max_hops=1
zynq_pm_remap_ocm: OCM pool is not available
zynq_pm_suspend_init: Unable to map OCM.
Registering SWP/SWPB emulation handler
input: gpio-keys as /devices/soc0/gpio-keys/input/input0
rtc-pcf8563 5-0051: setting system clock to 2017-09-15 14:39:34 UTC (1505486374)
of_cfs_init
of_cfs_init: OK
ALSA device list:
  No soundcards found.
mmc0: new high speed SDHC card at address aaaa
Freeing unused kernel memory: 1024K (c0900000 - c0a00000)
INIT: mmcblk0: mmc0:aaaa SS08G 7.40 GiB
 mmcblk0: p1 p2
version 2.88 booting
EXT4-fs (mmcblk0p2): recovery complete
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
Starting internet superserver: inetd.
INIT: Entering runlevel: 5
Configuring network interfaces... IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.24.1) started
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background
done.
Starting Dropbear SSH server: Generating key, this may take a while...
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQDMRmjIu3qRM1Viv6emSII3Cq7VPJ3Apf7KZvONpPDnS0GBqBPRaK8j0is1dG/U4kKB18M8+znGCaTfMvcQVkpRYsGw/HGRAnYIB1bMyzSFKRKCbNLYK+RtAcwZKg7NT9HqwSjAn0D5ovUtIL6mEAxjEGJHwTjPFZlW62SX6vyEuQE8WCtH99HrErVAhhvEwZ0N6kl0H8XbfdXnMBRXGpbLxgstZpn8hnj1NsbSoi1rBZp1bRau1Hp+g8q9LSA4Side8wu/ow40dE/O6OJPCQFHbiODCGS+p9538PIF0g9f8yGRhqMLmlWYyLKLMlRg09NXX7UxR14LpV0OXU6g5JRl [email protected]zynq7
Fingerprint: md5 63:7c:dd:d5:af:05:b4:37:ba:ee:16:01:ab:26:4e:ee
dropbear.
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2016.4 zc702-zynq7 /dev/ttyPS0

zc702-zynq7 login: root
[email protected]:~# pwd
/home/root
[email protected]:~#

End

时间: 2024-10-06 21:25:01

Zynq ZC702平台 QSPI + eMMC实现的相关文章

ZYNQ 7000平台UDP数据包(1字节或2字节)校验和Checksum错误0xFFFF解决方案(linux+vxworks6.9平台)

在赛灵思ZYNQ 7000平台,使用UDP方式发送1字节或者2字节数据时,校验和为错误值0xffff,接收机无法正常接收ZYNQ7000平台发送的数据,本人已经找到该问题的解决方案,有该问题的朋友可以通过邮箱[email protected]与我联系,联系时请详细描述你的环境,针对该咨询提供的问题解决方案会收取一定的费用,费用不会太高,现在是知识付费的年代,希望各位理解,同时如果能够解决您的问题,也是为你节约了开支.我会及时回复邮件的.具体事项可以邮件沟通[email protected].

zynq板卡学习资料:基于zynq XC7Z100 FMC接口通用计算平台367

基于zynq XC7Z100 FMC接口通用计算平台 一.板卡概述 本板卡基于Xilinx公司的FPGA XC7Z100 FFG 9000 芯片, 该平台为设计和验证应用程序提供了一个完整的开发平台.该平台使设计师能够更加简单进行高性能的原型设计,并且通过FMC HPC扩展槽提供可扩展性和满足客户定制需求. 二.基础接口和性能 使用 Zynq-7000 SoC  XC7Z100对嵌入式应用进行快速原型设计以实现优化 支持包含 Dual ARM Cortex-A9 核处理器的嵌入式处理 PS 端3

大于16MB的QSPI存放程序引起的ZYNQ重启风险

ZYNQ芯片是近两年比较流行的片子,双ARM+FPGA,在使用分立FPGA和CPU的场合很容易替代原来的分立器件. ZYNQ可以外接QSPI FLASH作为程序的存储介质. QSPI和SPI flash是串行接口的NOR FLASH,在设计支持,容量都比较小,所以协议中只留了3Bytes寻址,也就是最大16MB空间.但是随着工艺和技术的提升,现在32MB.64MB,甚至128MB和更大容量的SPI/QSPI flash都出现了. 以32MB为例,当需要访问大于16MB的地址是,新的器件提供了两种

小白初学zedboard 1 (遇到问题求教)

到网上查了一下,zedboard的资料好多,也看了好多,但还是不知道从哪入手...一步一步试着做好了,错了再纠正. 首先,我想先做PL实现读写DDR3. 参见:@超群天晴 http://www.cnblogs.com/surpassal/ 使用自带外设IP让ARM PS访问FPGA,我是想实现FPGA访问DDR3.都是使用自带外设IP进行通信,应该差不多.所以试着做,如下:(将步骤写在下面,犯的错误也容易发现) 1. 创建硬件工程:按照一步一步学zedboard & zynq(三) 启动XPS,

Linux双核SMP系统启动流程(Zynq-ARM-CortexA9)

转载:http://blog.chinaunix.net/uid-20648445-id-3329217.html 1:资料附录:    <ug585-Zynq-7000-TRM.pdf>                            xilinx zynq 7000技术参考手册    <ug821-zynq-7000-swdev.pdf>                          xilinx zynq 7000软件开发手册    <ug925-zynq-z

基于zedBoard的手势识别及桌面操控系统_项目论文

基于zedBoard的手势识别及桌面操控系统 山东大学信息学院集成电路 Sorin 目录 基于zedBoard的手势识别及桌面操控系统........................................................................ 1 综述..........................................................................................................

Zynq Qspi控制器应用笔记

Zynq Qspi控制器应用笔记 Hello,panda 1 Zynq Qspi控制器 Zynq Qspi控制器支持三种模式:I/O模式.线性地址模式和传统SPI模式,其中线性地址模式双片选支持最大的线性地址空间为32MB,可通过PS DMA读取. 1.1 线性地址模式 线性地址模式只可从Qspi Flash中读数.在配置QSPI BOOT时,BOOT ROM工作在线性地址模式,且访问时钟为ARM接入的晶振时钟,因此在选用晶振时频率不能大于Flash的最高访问时钟频率. 线性地址模式下IO可以配

SylixOS Zynq平台私有中断绑定

1. 概述 本篇主要介绍在Zynq平台编写中断相关的驱动程序时,涉及CPU私有中断的相关绑定办法. 2. 私有中断简介 私有中断是多核CPU上特有的中断,私有中断只能被其所有者核心获取和响应,不会被其他核发现.常见的私有中断有全局定时器,私有看门狗定时器,私有定时器等,Zynq平台上还有来自PL的FIQ\IRQ. 3. 私有中断的绑定方法 3.1      常规共享中断绑定 Zynq平台使用的是GIC通用中断框架,常规的共享中断绑定和普通的中断绑定没有区别,在SylixOS上直接调用API_In

基于Zynq平台的EtherCAT主站方案实现

作者:陈秋苑 谢晓锋 陈海焕 广州虹科电子科技有限公司 摘 要:EtherCAT 是开放的实时以太网通讯协议,由德国倍福自动化有限公司研发.EtherCAT 具有高性能.低成本.容易使用等特点,目前在工业自动化领域有着广泛的应用.Zynq-7000 是赛灵思公司(Xilinx)推出的行业第一个全可编程 SoC 产品, 它将双核 ARM Cortex-A9 处理器,低功耗可编程逻辑以及常用的外设紧密集成在一起.ZedBoard 是基于 XC7Z020 器件的低成本开发板,此板可以运行基于 Linu