熟悉nvme 协议是深入理解spdk 代码的基础。

重要寄存器

下面寄存器都是位于pcie memory space, bar[0/1] 空间。

Offset 24h: AQA – Admin Queue Attributes

The Admin Submission Queue’s priority is determined by the arbitration mechanism selected, refer to section 4.11. The Admin Submission Queue and Admin Completion Queue are required to be in physically contiguous memory.

Offset 28h: ASQ – Admin Submission Queue Base Address

This register defines the base memory address of the Admin Submission Queue.

Offset 30h: ACQ – Admin Completion Queue Base Address

This register defines the base memory address of the Admin Completion Queue.

上面queue中的每个entry指向的地址落在controller memroy buffer. 就是下面下面两个寄存器相关的区域。

Offset 38h: CMBLOC – Controller Memory Buffer Location

This optional register defines the location of the Controller Memory Buffer (refer to section 4.7). If CMBSZ is 0, this register is reserved.

Offset 3Ch: CMBSZ – Controller Memory Buffer Size

This optional register defines the size of the Controller Memory Buffer (refer to section 4.7). If the controller does not support the Controller Memory Buffer feature then this register shall be cleared to 0h.

重要数据结构

nvme 重要的数据结构包括submit/completion queue 、scatter/gather list、completion queue entry、controller memroy buffer、name space list、controller list; 命令仲裁机制；

nvme queue

队列特点

总体来说有两个特点：
submit / complete queue 是生产区消费者模型；
queue 以循环队列的数据结构关联；

队列长度

受谁决定：indicated in a 16-bit 0’s based field that indicates the number of slots in the queue
最小长度：2 slots;
IO submit/completion queue最大长度：64K slots;
Admin submit/completion queue最多长度：4K slots;

队列优先级

If the weighted round robin with urgent priority class arbitration mechanism is supported, then host software may assign a queue priority service class of Urgent, High, Medium or Low. If the weighted round robin with urgent priority class arbitration mechanism is not supported, then the priority setting is not used and is ignored by the controller.

队列标识符

创建的时候，需要指定一个16 bit 的标识符；

原文地址：http://blog.51cto.com/xiamachao/2351086