VERILOG:
case(a)
1‘b0:
begin
end
1‘b1:
begin
end
endcase
if()
begin
end
else
begin
if()
begin
end
else
begin
end
end
MATLAB:
switch(a),case(1),b=1;case(2),b=2;otherwise,b=3;end
分支语句横向对比
时间: 2024-10-25 05:59:24
VERILOG:
case(a)
1‘b0:
begin
end
1‘b1:
begin
end
endcase
if()
begin
end
else
begin
if()
begin
end
else
begin
end
end
MATLAB:
switch(a),case(1),b=1;case(2),b=2;otherwise,b=3;end
分支语句横向对比