TI_DSP_corePac_带宽管理 - 2(举例)

MDMAARBU:

The master DMA arbitration control register (MDMAARBU) controls the priority levels of MDMA requests going out of CorePac. It controls the priority levels used by the L2 memory
controller when sending requests to XMC.

When sending requests external to CorePac, L2 memory controller picks one of two priority values to send to XMC. For normal-priority requests, it uses the value ofMDMAARBU.PRI.
For urgent-priority requests, it uses the value of MDMAARBU.UPRI. Most L2 memory controller requests to XMC are not urgent.

Only the following request types are urgent requests:

? L1D read miss(L1D读niss，当然要从L2中去取数据，比较紧急，否则程序没法运行)

? L1P fetch for a branch target

? Critical subline of an L2 allocate

SDMAARBU:

这里只需设置SDMAARBDU寄存器的MAXWAIT域，即最大等待时间。该寄存器没有PRI域（优先级），因为优先级由外设（如FFTC,AIF2等）设置（外设提供设计的仲裁寄存器），因为是外设在访问slave，所以他们知道应该采用什么样的优先级。

TI_DSP_corePac_带宽管理 - 2(举例)