VHDL之concurrent之generate

GENERATE

  It is another concurrent statement (along with operators and WHEN). It is equivalent to the sequential statement LOOP in the sense that it

allows a section of code to be repeated a number of times, thus creating several instances of the same assignments.

  FOR / GENERATE:  notice that GENERATE must be labeled.

label: FOR identifier IN range GENERATE
  (concurrent assignments)
END GENERATE;

  IF/GENERATE

  An irregular form is also available, which uses IF/GENERATE (with an IF equivalent; recall that originally IF is a sequential statement). Here ELSE is not allowed.  

label1: FOR identifier IN range GENERATE
  ...
label2: IF condition GENERATE
  (concurrent assignments)
END GENERATE;
...
END GENERATE;

Example 1

SIGNAL x: BIT_VECTOR (7 DOWNTO 0);
SIGNAL y: BIT_VECTOR (15 DOWNTO 0);
SIGNAL z: BIT_VECTOR (7 DOWNTO 0);
...
G1: FOR i IN x‘RANGE GENERATE
  z(i) <= x(i) AND y(i+8);
END GENERATE;

Example 2  Vector Shifter

  The output vector must be a shifted version of the input vector, with twice its width and an amount of shift speci?ed by another input.

For example, if the input bus has width 4, and the present value is ‘‘1111’’, then the output should be one of the lines of the following

matrix (the original vector is underscored):

  row(0): 0 0 0 0 1 1 1 1

  row(1): 0 0 0 1 1 1 1 0

  row(2): 0 0 1 1 1 1 0 0

  row(3): 0 1 1 1 1 0 0 0

  row(4): 1 1 1 1 0 0 0 0

1 ------------------------------------------------
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ------------------------------------------------
5 ENTITY shifter IS
6 PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
7     sel: IN INTEGER RANGE 0 TO 4;
8     outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
9 END shifter;
10 ------------------------------------------------
11 ARCHITECTURE shifter OF shifter IS
12   SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);
13   TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;
14   SIGNAL row: matrix;
15 BEGIN
16   row(0) <= "0000" & inp;
17   G1: FOR i IN 1 TO 4 GENERATE
18     row(i) <= row(i-1)(6 DOWNTO 0) & ‘0‘;
19   END GENERATE;
20   outp <= row(sel);
21 END shifter;
22 ------------------------------------------------
时间: 2024-10-10 07:17:10

VHDL之concurrent之generate的相关文章

VHDL之concurrent之when

WHEN (simple and selected) It is one of the fundamental concurrent statements (along with operators and GENERATE). It appears in two forms: WHEN / ELSE (simple WHEN) and WITH / SELECT / WHEN (selected WHEN). 1) WHEN / ELSE: assignment WHEN condition

VHDL之concurrent之operators

Using operators Operators can be used to implement any combinational circuit. However, as will become apparent later, complex circuits are usually easier to write using sequential code, even if the circuit does not contain sequential logic. Example M

Oracle E-Business Suite Maintenance Guide Release 12.2(Patching Procedures)

更多内容参考: http://docs.oracle.com/cd/E51111_01/current/acrobat/122ebsmt.zip Preparing for Patching For patches that have manual steps, the patch readme file instructs you to use Oracle Patch Application Assistant (PAA) to create customized instructions

how to forget about delta cycles for RTL design

A delta cycle is a VHDL construct used to makeVHDL, a concurrent language, executable on asequential computer. For RTL design, you can adopt some simple rules andforget about delta cycles. For testbenches, often you must have a good understandingof w

VHDL基础1

Description Structure 一个可综合的VHDL描述中一般由3部分组成:LIBRARY declarations.ENTITY.ARCHITECTURE Library(库)用来设计重用和代码共享,使代码结构更清晰 1 LIBRARY library_name; 2 USE library_name.package_name.package_parts; 常用的三个Libray:ieee.std.work 其中std.work是默认可见的,不需声明,ieee需要明确的声明 Ent

ISE中如何将自己的verilog源代码.v或VHDL源代码.vhd封装打包成IP核?

=======================第一篇======================= 如何将自己写的verilog模块封装成IP核 将你的设计制作成BlackBox,也就是网表文件,这样别人看不到你的设计但是可以调用你的模块了.详细的参考信息如下: 1. 什么是BlackBox - 一个大的设计中可以用到一系列网表文件作为输入的一部分而并不全部使用HDL文件.当综合这个大设计时综合器不需要知道这个网表文件是怎样实现的,而只需要知道它的输入输出接口就可以了.这样的网表就称为黑盒子,因

Optimizing concurrent accesses in a directory-based coherency protocol

In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated wi

ConCurrent in Practice小记 (2)

Java-ConCurrent2.html :first-child{margin-top:0!important}img.plugin{box-shadow:0 1px 3px rgba(0,0,0,.1);border-radius:3px}iframe{border:0}figure{-webkit-margin-before:0;-webkit-margin-after:0;-webkit-margin-start:0;-webkit-margin-end:0}kbd{border:1p

Architectures for concurrent graphics processing operations

BACKGROUND 1. Field The present invention generally relates to rendering two-dimension representations from three-dimensional scenes, and more particularly to using ray tracing for accelerated rendering of photo-realistic two-dimensional representati