system_stm32f4xx.c：This file contains the system clock configuration for STM32F4xx devices.
1 /** 2 ****************************************************************************** 3 * @file system_stm32f4xx.c 4 * @author MCD Application Team 5 * @version V1.4.0 6 * @date 04-August-2014 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 8 * This file contains the system clock configuration for STM32F4xx devices. 9 * 10 * 1. This file provides two functions and one global variable to be called from 11 * user application: 12 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 13 * and Divider factors, AHB/APBx prescalers and Flash settings), 14 * depending on the configuration made in the clock xls tool. 15 * This function is called at startup just after reset and 16 * before branch to main program. This call is made inside 17 * the "startup_stm32f4xx.s" file. 18 * 19 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 20 * by the user application to setup the SysTick 21 * timer or configure other parameters. 22 * 23 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 24 * be called whenever the core clock is changed 25 * during program execution. 26 * 27 * 2. After each device reset the HSI (16 MHz) is used as system clock source. 28 * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to 29 * configure the system clock before to branch to main program. 30 * 31 * 3. If the system clock source selected by user fails to startup, the SystemInit() 32 * function will do nothing and HSI still used as system clock source. User can 33 * add some code to deal with this issue inside the SetSysClock() function. 34 * 35 * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define 36 * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or 37 * through PLL, and you are using different crystal you have to adapt the HSE 38 * value to your own configuration. 39 * 40 * 5. This file configures the system clock as follows: 41 *============================================================================= 42 *============================================================================= 43 * Supported STM32F40xxx/41xxx devices 44 *----------------------------------------------------------------------------- 45 * System Clock source | PLL (HSE) 46 *----------------------------------------------------------------------------- 47 * SYSCLK(Hz) | 168000000 48 *----------------------------------------------------------------------------- 49 * HCLK(Hz) | 168000000 50 *----------------------------------------------------------------------------- 51 * AHB Prescaler | 1 52 *----------------------------------------------------------------------------- 53 * APB1 Prescaler | 4 54 *----------------------------------------------------------------------------- 55 * APB2 Prescaler | 2 56 *----------------------------------------------------------------------------- 57 * HSE Frequency(Hz) | 25000000 58 *----------------------------------------------------------------------------- 59 * PLL_M | 25 60 *----------------------------------------------------------------------------- 61 * PLL_N | 336 62 *----------------------------------------------------------------------------- 63 * PLL_P | 2 64 *----------------------------------------------------------------------------- 65 * PLL_Q | 7 66 *----------------------------------------------------------------------------- 67 * PLLI2S_N | NA 68 *----------------------------------------------------------------------------- 69 * PLLI2S_R | NA 70 *----------------------------------------------------------------------------- 71 * I2S input clock | NA 72 *----------------------------------------------------------------------------- 73 * VDD(V) | 3.3 74 *----------------------------------------------------------------------------- 75 * Main regulator output voltage | Scale1 mode 76 *----------------------------------------------------------------------------- 77 * Flash Latency(WS) | 5 78 *----------------------------------------------------------------------------- 79 * Prefetch Buffer | ON 80 *----------------------------------------------------------------------------- 81 * Instruction cache | ON 82 *----------------------------------------------------------------------------- 83 * Data cache | ON 84 *----------------------------------------------------------------------------- 85 * Require 48MHz for USB OTG FS, | Disabled 86 * SDIO and RNG clock | 87 *----------------------------------------------------------------------------- 88 *============================================================================= 89 *============================================================================= 90 * Supported STM32F42xxx/43xxx devices 91 *----------------------------------------------------------------------------- 92 * System Clock source | PLL (HSE) 93 *----------------------------------------------------------------------------- 94 * SYSCLK(Hz) | 180000000 95 *----------------------------------------------------------------------------- 96 * HCLK(Hz) | 180000000 97 *----------------------------------------------------------------------------- 98 * AHB Prescaler | 1 99 *----------------------------------------------------------------------------- 100 * APB1 Prescaler | 4 101 *----------------------------------------------------------------------------- 102 * APB2 Prescaler | 2 103 *----------------------------------------------------------------------------- 104 * HSE Frequency(Hz) | 25000000 105 *----------------------------------------------------------------------------- 106 * PLL_M | 25 107 *----------------------------------------------------------------------------- 108 * PLL_N | 360 109 *----------------------------------------------------------------------------- 110 * PLL_P | 2 111 *----------------------------------------------------------------------------- 112 * PLL_Q | 7 113 *----------------------------------------------------------------------------- 114 * PLLI2S_N | NA 115 *----------------------------------------------------------------------------- 116 * PLLI2S_R | NA 117 *----------------------------------------------------------------------------- 118 * I2S input clock | NA 119 *----------------------------------------------------------------------------- 120 * VDD(V) | 3.3 121 *----------------------------------------------------------------------------- 122 * Main regulator output voltage | Scale1 mode 123 *----------------------------------------------------------------------------- 124 * Flash Latency(WS) | 5 125 *----------------------------------------------------------------------------- 126 * Prefetch Buffer | ON 127 *----------------------------------------------------------------------------- 128 * Instruction cache | ON 129 *----------------------------------------------------------------------------- 130 * Data cache | ON 131 *----------------------------------------------------------------------------- 132 * Require 48MHz for USB OTG FS, | Disabled 133 * SDIO and RNG clock | 134 *----------------------------------------------------------------------------- 135 *============================================================================= 136 *============================================================================= 137 * Supported STM32F401xx devices 138 *----------------------------------------------------------------------------- 139 * System Clock source | PLL (HSE) 140 *----------------------------------------------------------------------------- 141 * SYSCLK(Hz) | 84000000 142 *----------------------------------------------------------------------------- 143 * HCLK(Hz) | 84000000 144 *----------------------------------------------------------------------------- 145 * AHB Prescaler | 1 146 *----------------------------------------------------------------------------- 147 * APB1 Prescaler | 2 148 *----------------------------------------------------------------------------- 149 * APB2 Prescaler | 1 150 *----------------------------------------------------------------------------- 151 * HSE Frequency(Hz) | 25000000 152 *----------------------------------------------------------------------------- 153 * PLL_M | 25 154 *----------------------------------------------------------------------------- 155 * PLL_N | 336 156 *----------------------------------------------------------------------------- 157 * PLL_P | 4 158 *----------------------------------------------------------------------------- 159 * PLL_Q | 7 160 *----------------------------------------------------------------------------- 161 * PLLI2S_N | NA 162 *----------------------------------------------------------------------------- 163 * PLLI2S_R | NA 164 *----------------------------------------------------------------------------- 165 * I2S input clock | NA 166 *----------------------------------------------------------------------------- 167 * VDD(V) | 3.3 168 *----------------------------------------------------------------------------- 169 * Main regulator output voltage | Scale1 mode 170 *----------------------------------------------------------------------------- 171 * Flash Latency(WS) | 2 172 *----------------------------------------------------------------------------- 173 * Prefetch Buffer | ON 174 *----------------------------------------------------------------------------- 175 * Instruction cache | ON 176 *----------------------------------------------------------------------------- 177 * Data cache | ON 178 *----------------------------------------------------------------------------- 179 * Require 48MHz for USB OTG FS, | Disabled 180 * SDIO and RNG clock | 181 *----------------------------------------------------------------------------- 182 *============================================================================= 183 *============================================================================= 184 * Supported STM32F411xx devices 185 *----------------------------------------------------------------------------- 186 * System Clock source | PLL (HSI) 187 *----------------------------------------------------------------------------- 188 * SYSCLK(Hz) | 100000000 189 *----------------------------------------------------------------------------- 190 * HCLK(Hz) | 100000000 191 *----------------------------------------------------------------------------- 192 * AHB Prescaler | 1 193 *----------------------------------------------------------------------------- 194 * APB1 Prescaler | 2 195 *----------------------------------------------------------------------------- 196 * APB2 Prescaler | 1 197 *----------------------------------------------------------------------------- 198 * HSI Frequency(Hz) | 16000000 199 *----------------------------------------------------------------------------- 200 * PLL_M | 16 201 *----------------------------------------------------------------------------- 202 * PLL_N | 400 203 *----------------------------------------------------------------------------- 204 * PLL_P | 4 205 *----------------------------------------------------------------------------- 206 * PLL_Q | 7 207 *----------------------------------------------------------------------------- 208 * PLLI2S_N | NA 209 *----------------------------------------------------------------------------- 210 * PLLI2S_R | NA 211 *----------------------------------------------------------------------------- 212 * I2S input clock | NA 213 *----------------------------------------------------------------------------- 214 * VDD(V) | 3.3 215 *----------------------------------------------------------------------------- 216 * Main regulator output voltage | Scale1 mode 217 *----------------------------------------------------------------------------- 218 * Flash Latency(WS) | 3 219 *----------------------------------------------------------------------------- 220 * Prefetch Buffer | ON 221 *----------------------------------------------------------------------------- 222 * Instruction cache | ON 223 *----------------------------------------------------------------------------- 224 * Data cache | ON 225 *----------------------------------------------------------------------------- 226 * Require 48MHz for USB OTG FS, | Disabled 227 * SDIO and RNG clock | 228 *----------------------------------------------------------------------------- 229 *============================================================================= 230 ****************************************************************************** 231 * @attention 232 * 233 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 234 * 235 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 236 * You may not use this file except in compliance with the License. 237 * You may obtain a copy of the License at: 238 * 239 * http://www.st.com/software_license_agreement_liberty_v2 240 * 241 * Unless required by applicable law or agreed to in writing, software 242 * distributed under the License is distributed on an "AS IS" BASIS, 243 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 244 * See the License for the specific language governing permissions and 245 * limitations under the License. 246 *
时间： 2024-10-10 13:54:37