VHDL之User-defined data types

VHDL allows the user to define own data types.

1　user-defined integer types　　

-- This is indeed the pre-defined type integer
type integer is range -2147483647 to +2147483647;

-- indeed the pre-defined type natural
type natural is range 0 to +2147483647;

-- user-defined subset of integers
type my_integer is range -32 to 32;

-- user-defined subset of integers or naturals
type student_grade is range 0 to 100;

2　user-defined enumerated types

-- This is indeed the pre-defined type BIT
type bit is (‘0‘,‘1‘);

-- user-defined subset of std_logic
type my_logic is (‘0‘,‘1‘,‘Z‘);

-- indeed the pre-defined type of BIT_VECTOR
-- range <> is used to indicate that the range is unconstrained
-- NATURAL range <> indicate the range must fall within the NATURAL range
type BIT_VECTOR is array (NATURAL range <>) of BIT;

-- an enumerated data type, typical of finte state machines
type state is (idle, forward, backward, stop);

-- another enumerated data type
type color is (red, green, blue, white)

　　The encoding of enumerated types is done sequentially and automatically. For example, for the type color above, two bits are necessary (there are four states), being ‘‘00’’ assigned to the ?rst state (red), ‘‘01’’ to the second (green), ‘‘10’’ to the next (blue), and ?nally ‘‘11’’ to the last state (white).