omsp430ik fpga实现

为了验证omsp430ik的FPGA程序运行是否正确，写了一个很简单的流水灯程序，通过P1口驱动。

int main()
{
  int i;
  WDTCTL  = 0x5a80;

  P1DIR = 0xff;
  while(1)
    for(i=0;i<8;i++)
    {
      P1OUT = (1<<i);
      delayms(256);
    }
}

我目前手上的板子是Crazy Bingo的《VIP_Board Mini 》，LED并不直接连到FPGA管教，是通过74HC595芯片转换的。所以还需要写一个并转串的程序。FPGA资料包已经有该模块的驱动程序，不过还是自己写一个吧，自己动手，丰衣足食。

`timescale 1ns/1ns
module led_drv
(
    //74hc595 interface
    output            sdat,
    output            sclk,
    output  reg slatch,

    input    [7:0]    pdata,
    input              clk,
    input              rst_n
);

reg   [3:0] count;
reg   [7:0] pdata_r;
reg         enable;

wire  [2:0] bitcnt = count[3:1];
wire        update  = (pdata_r != pdata);

//  data change detect
always @(posedge clk) pdata_r  <=  pdata;

always @(posedge clk or negedge rst_n)
  if(!rst_n)            enable  <=  1‘b1;
  else if(count==4‘hf)  enable <= 1‘b0;
  else if(update)       enable <= 1‘b1;

always @(posedge clk or negedge rst_n)
  if(!rst_n)        count <= 0;
  else if(!enable)  count <= 0;
  else              count <= count + 1‘b1;

assign  sdat  = pdata[bitcnt];
assign  sclk  = count[0];

always @(posedge clk) slatch  <=  (count==4‘hf);

endmodule

例化

// led drv
led_drv u_led_74595_drv
(
    //74hc595 interface
    .sdat   (sdat),
    .sclk   (sclk),
    .slatch (slatch),

    .pdata  (gpio1_dout),
    .clk    (mclk),
    .rst_n  (~puc)
);

仿真波形：

流水灯控制 P1口波形

74HC595波形：

1：

2：

quaruts综合报告，

文件列表

set_global_assignment -name SEARCH_PATH ../../../src/include
set_global_assignment -name VERILOG_FILE ../../../src/include/openMSP430_defines.v
set_global_assignment -name VERILOG_FILE ../../../src/include/openMSP430_undefines.v
set_global_assignment -name VERILOG_FILE ../../../src/include/timescale.v
set_global_assignment -name VERILOG_FILE ../../../src/led_drv/led_drv.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430/omsp430.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430/omsp_alu.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430/omsp_execution_unit.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430/omsp_frontend.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430/omsp_mem_backbone.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430/omsp_register_file.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430ikmcu/omsp430ikmcu.v
set_global_assignment -name VERILOG_FILE ../../../src/omsp430ikmcu/omsp430ik_sys.v
set_global_assignment -name VERILOG_FILE ../../../src/periph/gpio.v
set_global_assignment -name VERILOG_FILE ../../../src/periph/template_periph_8b.v
set_global_assignment -name VERILOG_FILE ../../../src/uart/uart.v
set_global_assignment -name VERILOG_FILE ../../../src/uart/uart_rx.v
set_global_assignment -name VERILOG_FILE ../../../src/uart/uart_tx.v
set_global_assignment -name VERILOG_FILE ../mem/alt_rom4kx16.v
set_global_assignment -name VERILOG_FILE ../mem/omsp430_dmem.v
set_global_assignment -name VERILOG_FILE ../mem/omsp430_pmem.

FPGA运行效果1；

2