序列检测101 状态机实现

module jiance #

(
parameter CNT_NUM = 12500000
)

( clk,rst_n,data, clk_1hz,out);
input clk,rst_n,data;
output reg out,clk_1hz;
reg [1:0] cstate,nstate;
parameter s0=2‘b00,
s1=2‘b01,
s2=2‘b10;

reg [24:0] cnt = 25‘d0;
//reg clk_1hz = 1‘b0;
[email protected](posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 25‘d0;
clk_1hz <= 1‘b0;
end else if(cnt>=(CNT_NUM-1)) begin
cnt <= 25‘d0;
clk_1hz <= ~clk_1hz;
end else begin
cnt <= cnt + 25‘d1;
end
end
[email protected](posedge clk_1hz or negedge rst_n)
if(!rst_n) cstate<=s0;
else cstate<=nstate;
[email protected](posedge clk_1hz or negedge rst_n)
begin
if(!rst_n)nstate<=s0;
else begin

case(cstate)
s0:nstate <=(data)?s1:s0;
s1:nstate<=(data)?s1:s2;
s2:nstate<=(data)?s1:s0;
default:nstate<=s0;
endcase
end
end
[email protected](posedge clk_1hz or negedge rst_n)
begin
if(!rst_n)out<=0;
else
case(nstate)
s0:out<=0;
s1:out<=0;
s2:begin if(data==1)out<=1;
else out<=0;end
default:out<=0;
endcase
end
endmodule