verilog 1

 1 module fa_str(a,b,cin,sum,cout);
 2     input a,b,cin;
 3     output sum,cout;
 4     wire s1,t1,t2,t3;
 5     xor
 6         ux1(s1,a,b),
 7         ux2(sum,s1,cin);
 8     and
 9         ua1(t3,a,b),
10         ua2(t2,b,cin),
11         ua3(t1,a,cin);
12     or
13         uo1(cout,t1,t2,t3);
14 endmodule