| ARM Cortex-M |
Thumb | Thumb-2 | Hardware multiply |
Hardware divide |
Saturated math |
DSP extensions |
Floating-point | ARM architecture |
Core architecture |
|---|---|---|---|---|---|---|---|---|---|
| Cortex-M0 |
Most | Subset | 1 or 32 cycle | No | No | No | No | ARMv6-M |
Von Neumann |
| Cortex-M0+ |
Most | Subset | 1 or 32 cycle | No | No | No | No | ARMv6-M |
Von Neumann |
| Cortex-M1 |
Most | Subset | 3 or 33 cycle | No | No | No | No | ARMv6-M |
Von Neumann |
| Cortex-M3 |
Entire | Entire | 1 cycle | Yes | Yes | No | No | ARMv7-M |
Harvard |
| Cortex-M4 |
Entire | Entire | 1 cycle | Yes | Yes | Yes | Optional | ARMv7E-M |
Harvard |
| Cortex-M4F | Entire | Entire | 1 cycle | Yes | Yes | Yes | Yes | ARMv7E-M | Harvard |
Note: The Cortex-M0 / M0+ / M1 doesn‘t include these Thumb instructions:
CBZ, CBNZ, IT; nor does it include a divide instruction.
Note: The Cortex-M0 / M0+ / M1 only include these Thumb-2 instructions:
DMB, DSB, ISB, MRS, MSR.
Note: If a smaller silicon die size is required, the Cortex-M0 / M0+ / M1
can implement a smaller and slower multiply instruction.
All four Cortex-M cores implement a common instruction subset that consists of:
Thumb subset, Thumb-2 subset, and multiply.
The Cortex-M0 / M0+ / M1 include all older Thumb instructions,
except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture.
The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions
(BL, DMB, DSB, ISB, MRS, MSR).
The Cortex-M0 / M0+ / M1 were designed to be the smallest size possible,
thus having the fewest instructions of the Cortex-M family.
The Cortex-M3 adds 3 Thumb instructions and all Thumb-2 instructions,
plus a 10-12 cycle hardware divide and saturated math instructions.
The Cortex-M4 adds DSP instructions and an optional single-precisionfloating-point unit.
If the Cortex-M4 has the floating point unit, then it is known as the Cortex-M4F.
| Instructions | Instruction size |
Cortex M0 |
Cortex M0+ |
Cortex M1 |
Cortex M3 |
Cortex M4 |
Cortex M4F |
|---|---|---|---|---|---|---|---|
| ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STMIA, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD | 16-bit | Yes | Yes | Yes | Yes | Yes | Yes |
| BL, DMB, DSB, ISB, MRS, MSR | 32-bit | Yes | Yes | Yes | Yes | Yes | Yes |
| CBNZ, CBZ, IT | 16-bit | No | No | No | Yes | Yes | Yes |
| ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, CLZ, CMN, CMP, DBG, EOR, LDC, LDMA, LDMDB, LDR, LDRB, LDRBT, LDRD, LDREX, LDREXB, LDREXH, LDRH, LDRHT, LDRSB, LDRSBT, LDRSHT, LDRSH, LDRT, MCR, LSL, LSR, MLS, MCRR, MLA, MOV, MOVT, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SDIV, SEV, SMLAL, SMULL, SSAT, STC, STMDB, STR, STRB, STRBT, STRD, STREX, STREXB, STREXH, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UDIV, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD | 32-bit | No | No | No | Yes | Yes | Yes |
| PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16 | 32-bit | No | No | No | No | Yes | Yes |
| VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUB | 32-bit | No | No | No | No | No | Yes |