A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.
控制寄存器（Control Register）是用来修改或控制CPU特性的寄存器。它通常的功能包括：中断控制，地址模式转换，页面控制和并行控制。例如cr0寄存器的第0位（PE位）置位，系统将运行在保护模型下，否则运行在实模式下。
cr0
| Bit | Name | Full Name | Description |
|---|---|---|---|
| 31 | PG | Paging | If 1, enable paging and use the CR3 register, else disable paging（是否允许内存分页） |
| 30 | CD | Cache disable | Globally enables/disable the memory cache |
| 29 | NW | Not-write through | Globally enables/disable write-back caching |
| 18 | AM | Alignment mask | Alignment check enabled if AM set, AC flag (in EFLAGS register) set, and privilege level is 3 |
| 16 | WP | Write protect | Determines whether the CPU can write to pages marked read-only（root是否可写用户空间） |
| 5 | NE | Numeric error | Enable internal x87 floating point error reporting when set, else enables PC style x87 error detection |
| 4 | ET | Extension type | On the 386, it allowed to specify whether the external math coprocessor was an80287 or 80387 |
| 3 | TS | Task switched | Allows saving x87 task context upon a task switch only after x87 instruction used |
| 2 | EM | Emulation | If set, no x87 floating point unit present, if clear, x87 FPU present |
| 1 | MP | Monitor co-processor | Controls interaction of WAIT/FWAIT instructions with TS flag in CR0 |
| 0 | PE | Protected Mode Enable | If 1, system is in protected mode, else system is in real mode（实模式or保护模式） |
cr1
保留
cr2
Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory entry.
cr3
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine check exceptions.
| Bit | Name | Full Name | Description |
|---|---|---|---|
| 21 | SMAP | Supervisor Mode Access Protection Enable | If set, access of data in a higher ring generates a fault |
| 20 | SMEP | Supervisor Mode Execution Protection Enable | If set, execution of code in a higher ring generates a fault |
| 18 | OSXSAVE | XSAVE and Processor Extended States Enable | |
| 17 | PCIDE | PCID Enable | If set, enables process-context identifiers (PCIDs). |
| 14 | SMXE | Safer Mode Extensions Enable | see Trusted Execution Technology (TXT) |
| 13 | VMXE | Virtual Machine Extensions Enable | see Intel VT-x |
| 10 | OSXMMEXCPT | Operating System Support for Unmasked SIMD Floating-Point Exceptions | If set, enables unmasked SSE exceptions. |
| 9 | OSFXSR | Operating system support for FXSAVE and FXRSTOR instructions | If set, enables SSE instructions and fast FPU save & restore |
| 8 | PCE | Performance-Monitoring Counter enable | If set, RDPMC can be executed at any privilege level, else RDPMC can only be used in ring 0. |
| 7 | PGE | Page Global Enabled | If set, address translations (PDE or PTE records) may be shared between address spaces. |
| 6 | MCE | Machine Check Exception | If set, enables machine check interrupts to occur. |
| 5 | PAE | Physical Address Extension | If set, changes page table layout to translate 32-bit virtual addresses into extended 36-bit physical addresses. |
| 4 | PSE | Page Size Extension | If unset, page size is 4 KiB, else page size is increased to 4 MiB (or 2 MiB with PAE set). |
| 3 | DE | Debugging Extensions | If set, enables debug register based breaks on I/O space access |
| 2 | TSD | Time Stamp Disable | If set, RDTSC instruction can only be executed when in ring 0, otherwise RDTSC can be used at any privilege level. |
| 1 | PVI | Protected-mode Virtual Interrupts | If set, enables support for the virtual interrupt flag (VIF) in protected mode. |
| 0 | VME | Virtual 8086 Mode Extensions | If set, enables support for the virtual interrupt flag (VIF) in virtual-8086 mode. |
IA-32平台的Control Register（控制寄存器）