paper:synthesizable finite state machine design techniques using the new systemverilog 3.0 enhancements 之 standard verilog FSM conding styles(二段式)

1.Two always block style with combinational outputs(Good Style)

对应的代码如下:

2段式总结:

(1)the combinational always block sensitivity list is sensitve to changes on the state variable and all of the inputs referenced in the combinaltional always block.

这个实际中一般就用[email protected](*)就OK了。

(2)the combinaltional always block has a default next state assignments at the top of the always block

(3)default output assignments are made prior to the case statement(this eliminates latches and reduces the amount of code required to code the rest of the outputs in the case statement and hightlights

in the case statement exactly in which states the individual output(s) change).

开始所有的output and next state变量都要初始化默认值,否则会有latches产生(特别是当outputs比较多时,容易漏掉个别output singals)。

(4)in the states where the output assignment is not the default value assigned at the top of always block,the output assignment is only made once for each state.

每一个state,如果output输出不是默认值,仅仅被赋值一次。

(5)状态跳转的弧线(arc)个数与if-else-type语句个数相同。

(6)每一行只有一个next_state语句,方便阅读调试。

 default X-assignments common trick:

时间: 2024-10-04 20:30:20

paper:synthesizable finite state machine design techniques using the new systemverilog 3.0 enhancements 之 standard verilog FSM conding styles(二段式)的相关文章

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Three always block style with registered outputs(Good style)

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case语句中,对于state/next 矢量仅仅做了1-bit比较. parameter 值不是表示FSM的状态编码,而是表示state/next变量的索引.

paper:synthesizable finit state machine design techniques using the new systemverilog 3.0 enhancements之output encoded style with registered outputs(Good style)

把输出跟状态编码结合起来,即使可以省面积又是寄存器输出.但是没有讲解如何实现这种高效的编码.

paper:synthesizable finit state machine design techniques using the new systemverilog 3.0 enhancements之enhanced coding styles

1.ANSI style 的代码比较紧凑. 下面规范推荐,比较好. 下面是带有parameter的module header的完整规范 一般1bit ,大家都是wire signal1 = gen_signal1_logic; 这种写法.似乎也不是直接assign signal1=gen_signal1_logic,不声明wire signals;. 个人一般就用[email protected](*),觉得带个()这样1.易于跟seq的统一2.易于看到*.

paper:synthesizable finit state machine design techniques using the new systemverilog 3.0 enhancements之fsm summary

主要是1.不要用1段式写FSM 2.不要用状态编码写one-hot FSM ,要用索引编码写one-hot FSM.

paper:synthesizable finit state machine design techniques using the new systemverilog 3.0 enhancements之onehot coding styles(encoded-parameter style with registered outputs不推荐但是经常有人写这样的代码)

这样写法,不利与综合,case语句中比较也是full-vector比较.

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